Shuang Xie

A power and area efficient 65 nm CMOS delay line ADC for on-chip voltage sensing

Shuang Xie, Wai Tung Ng, Sida Amy Shen, 2012 .

A 0.02 nJ self-calibrated 65nm CMOS delay line temperature sensor

Shuang Xie, Wai Tung Ng, 2012, 2012 IEEE International Symposium on Circuits and Systems.

An all-digital self-calibrated delay-line based temperature sensor for VLSI thermal sensing and management

Shuang Xie, Wai Tung Ng, W. Ng, 2015, Integr..

Digital integrated temperature sensors for VLSI thermal management

Shuang Xie, Wai Tung Ng, W. Ng, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

Delay-line temperature sensors and VLSI thermal management demonstrated on a 60nm FPGA

Shuang Xie, Wai Tung Ng, W. Ng, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Compensation for Process and Temperature Dependency in a CMOS Image Sensor

Shuang Xie, Albert J. P. Theuwissen, 2019, Sensors.

A power and area efficient 65 nm CMOS delay line ADC for on-chip voltage sensing

Shuang Xie, Wai Tung Ng, Sida Amy Shen, 2012, 2012 IEEE International Conference on Electron Devices and Solid State Circuit (EDSSC).

A low power all-digital self-calibrated temperature sensor using 65nm FPGAs

Shuang Xie, Wai Tung Ng, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).