D. Fried

Predictive modeling of pattern-dependent etch effects in large-area fully-integrated 3D virtual fabrication

R. Patz, D. Fried, K. Greiner, 2014, 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

A million wafer, virtual fabrication approach to determine process capability requirements for an industry-standard 5nm BEOL two-level metal flow

D. Mocuta, D. Fried, C. J. Wilson, 2016, 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

22nm technology yield optimization using multivariate 3D virtual fabrication

B. Jagannathan, S. Furkay, S. Narasimha, 2013, 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

RMG nMOS 1st process enabling 10x lower gate resistivity in N7 bulk FinFETs

B. Parvais, S. Van Elshocht, A. Brand, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Integration and optimization of embedded-sige, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies

D. Greenlaw, H.-J. Engelmann, N. Kepler, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL

J. Gill, D. Mocuta, D. Greenlaw, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..