Robert M. Houle

A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction

Harold Pilo, Chad A. Adams, Igor Arsovski, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

1.4Gsearch/s 2-Mb/mm2 TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%

Igor Arsovski, Robert M. Houle, Akhilesh Patil, 2018, IEEE Journal of Solid-State Circuits.

Simple Statistical Analysis Techniques to Determine Optimum Sense Amp Set Times

Robert M. Houle, 2008, IEEE Journal of Solid-State Circuits.

12.4 1.4Gsearch/s 2Mb/mm2 TCAM using two-phase-precharge ML sensing and power-grid preconditioning to reduce Ldi/dt power-supply noise by 50%

Igor Arsovski, Robert M. Houle, Steven Burns, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

Algorithmic ternary content addressable memory (TCAM) for N-search / M-write operations

Igor Arsovski, Robert M. Houle, Michael T. Fragano, 2016 .

Simple Statistical Analysis Techniques to Determine Optimum Sense Amp Set Times

Robert M. Houle, 2008, IEEE J. Solid State Circuits.

Digital delay line clock shapers and multipliers

Robert M. Houle, Roland A. Bechade, 1995, IBM J. Res. Dev..

FP 15.6: A 480MHz RISC Microprocessor in a 0.12pm Le, CMOS Technology with Copper Interconnects

Robert M. Houle, C. Akrout, M. Canada, 1998 .

A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements

Carl Radens, Harold Pilo, Igor Arsovski, 2011, IEEE Journal of Solid-State Circuits.

A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements

Carl Radens, Harold Pilo, Igor Arsovski, 2011, 2011 IEEE International Solid-State Circuits Conference.