Chauchin Su

发表

Energy-Effective Sub-Threshold Interconnect Design Using High-Boosting Predrivers

Yingchieh Ho, Hungkai Chen, Chauchin Su, 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Analysis and Design of Wide-Band Digital Transmission in an Electrostatic-Coupling Intra-Body Communication System

Chien-Nan Jimmy Liu, Chauchin Su, Yuhwai Tseng, 2009, IEICE Trans. Commun..

desire to reduce (or eliminate) complex and in P1149.4 Environment

Shyh-Jye Jou, Chauchin Su, Yue-Tsang Chen, 1997 .

Oscillation ring based interconnect test scheme for SOC

Chauchin Su, Katherine Shu-Min Li, Chung-Len Lee, 2005, ASP-DAC.

Passive Reduced-Order Macro-Modeling for Linear Time-Delay Interconnect Systems

Chien-Nan Jimmy Liu, Chauchin Su, Wenliang Tseng, 2006, IEICE Trans. Electron..

Multilevel Full-Chip Routing With Testability and Yield Enhancement

Yao-Wen Chang, Chauchin Su, Katherine Shu-Min Li, 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Is IDDQ testing not applicable for deep submicron VLSI in year 2011?

Chauchin Su, Chih-Wen Lu, Chung-Len Lee, 2000, Proceedings of the Ninth Asian Test Symposium.

A 48.6-to-105.2 µW Machine Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Applications

Yingchieh Ho, Chauchin Su, Po-Yao Chang, 2014, IEEE Journal of Solid-State Circuits.

A methodology for fault model development for hierarchical linear systems

Chauchin Su, Chung-Len Lee, Jwu E. Chen, 2000, Proceedings of the Ninth Asian Test Symposium.

Random testing of interconnects in a boundary scan environment

Chauchin Su, 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults

Yao-Wen Chang, Chauchin Su, Katherine Shu-Min Li, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing

Chauchin Su, Chih-Wen Lu, Chung-Len Lee, 2002, J. Electron. Test..

Fault Diagnosis for Linear Analog Circuits

Chauchin Su, Chung-Len Lee, Jwu E. Chen, 2001, J. Electron. Test..

A scalable digitalized buffer for gigabit I/O

Chien-Nan Jimmy Liu, Chauchin Su, Hungwen Lu, 2008, 2008 IEEE Custom Integrated Circuits Conference.

A Scalable Digitalized Buffer for Gigabit I/O

Chien-Nan Jimmy Liu, Chauchin Su, Hungwen Lu, 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

1149.4 based on-line quiescent state monitoring technique [analog DFT]

Chauchin Su, Chih-Hu Wang, Wei-Juo Wang, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

Measurement and Evaluation of the Bioelectrical Impedance of the Human Body by Deconvolution of a Square Wave

Chien-Nan Jimmy Liu, Chauchin Su, Yuhwai Tseng, 2010, IEICE Trans. Inf. Syst..

Evaluation and Verification of Channel Transmission Characteristics of Human Body for Optimizing Data Transmission Rate in Electrostatic-Coupling Intra Body Communication System: A Comparative Analysis

Yingchieh Ho, Chauchin Su, Yuhwai Tseng, 2016, PloS one.

A unified approach to detecting crosstalk faults of interconnects in deep sub-micron VLSI

Chauchin Su, Katherine Shu-Min Li, Chung-Len Lee, 2004, 13th Asian Test Symposium.

An autonomous multiple module clock synchronization methodology for SoC

Chauchin Su, Shi-Dai Mai, Hong-Wen Lune, 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

A spread spectrum clock generator for SATA-II

Chauchin Su, Wei-Ta Chen, Hong-Wen Lune, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A Near-Threshold 480 MHz 78 µW All-Digital PLL With a Bootstrapped DCO

Yingchieh Ho, Chauchin Su, Yu-Sheng Yang, 2013, IEEE Journal of Solid-State Circuits.

Adaptive Two-Stage Fuzzy Temperature Control for an Electroheat System

Bore-Kuen Lee, Chien-Nan Jimmy Liu, Chauchin Su, 2009 .

Configuration free SoC interconnect BIST methodology

Chauchin Su, Wenliang Tseng, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

ECCSyn-A synthesis tool for ECC circuits

Chauchin Su, Jyrghong Wang, 1993, 1993 IEEE International Symposium on Circuits and Systems.

Finite State Machine Synthesis for At-Speed Oscillation Testability

Chauchin Su, Katherine Shu-Min Li, Jwu E. Chen, 2005, 14th Asian Test Symposium (ATS'05).

An I/sub DDQ/ based built-in concurrent test technique for interconnects in a boundary scan environment

Shyh-Jye Jou, Chauchin Su, Kychin Hwang, 1994, Proceedings., International Test Conference.

Multilevel Full-Chip Routing With Testability and Yield Enhancement

Yao-Wen Chang, Chauchin Su, Katherine Shu-Min Li, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Circuits design optimization using symbolic approach

Shyh-Jye Jou, Chauchin Su, Kou-Fong Liu, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

Impulse response fault model and fault extraction for functional level analog circuit diagnosis

Chauchin Su, Yue-Tsang Chen, Shenshung Chiang, 1995, J. Inf. Sci. Eng..

Test waveform shaping in mixed signal test bus by pre-equalization

Chauchin Su, Yue-Tsang Chen, 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

LDMOS Channel Thermometer Based on a Thermal Resistance Sensor for Balancing Temperature in Monolithic Power ICs

Yingchieh Ho, Chauchin Su, Ting-You Lin, 2017, Sensors.

Design of a Subthreshold-Supply Bootstrapped CMOS Inverter Based on an Active Leakage-Current Reduction Technique

Yingchieh Ho, Chauchin Su, Chiachi Chang, 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier

Chauchin Su, Chung-Len Lee, Jwu E. Chen, 2000, J. Inf. Sci. Eng..

A BIST methodology for iterative logic arrays

Chauchin Su, C. R. Kime, J. K. Lemke, 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

A linear optimal test generation algorithm for interconnect testing

Chauchin Su, 1998, ICCAD.

A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design

Shyh-Jye Jou, Chauchin Su, Chang-Yu Chen, 1995 .

BIST for Measuring Clock Jitter of Charge-Pump Phase-Locked Loops

Chauchin Su, Jen-Chien Hsu, 2008, IEEE Transactions on Instrumentation and Measurement.

A 0.5V/22 μW low power transceiver IC for use in ESC intra-body communication system

Yingchieh Ho, Chauchin Su, Yuhwai Tseng, 2016, 2016 International SoC Design Conference (ISOCC).

A novel LCD driver testing technique using logic test channels

Chauchin Su, Chih-Hu Wang, Wei-Juo Wang, 2003, ASP-DAC '03.

A 0.2–0.6 V ring oscillator design using bootstrap technique

Yingchieh Ho, Chauchin Su, Yu-Sheng Yang, 2011, IEEE Asian Solid-State Circuits Conference 2011.

Design of an All-Digital LVDS Driver

Chien-Nan Jimmy Liu, Chauchin Su, Hsin-Wen Wang, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

Intrinsic response extraction for the removal of the parasiticeffects in analog test buses

Chauchin Su, Yue-Tsang Chen, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Hardware efficient updating technique for LZW CODEC design

Chauchin Su, Chenq-Fan Yen, Jang-Chuang Yo, 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

Qualitative analysis of coupled transmission lines

Chauchin Su, Wenliang Tseng, Sonfu Yeh, 2003, 53rd Electronic Components and Technology Conference, 2003. Proceedings..

Parasitic effect removal for analog measurement in P1149.4 environment

Shyh-Jye Jou, Chauchin Su, Yue-Tsang Chen, 1997, Proceedings International Test Conference 1997.

Metrology for analog module testing using analog testability bus

Shyh-Jye Jou, Chauchin Su, Yue-Tsang Chen, 1996, Proceedings of International Conference on Computer Aided Design.

Fault diagnosis for linear analog circuits

Chauchin Su, Chung-Len Lee, Jwu E. Chen, 2000, Proceedings of the Ninth Asian Test Symposium.

Analog signal metrology for mixed signal ICs

Chauchin Su, Yue-Tsang Chen, Yi-Ren Cheng, 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

Equivalent circuits for the qualitative analysis of the transmission line reflection effects

Chauchin Su, Wenliang Tseng, Sonfu Yeh, 2002, Electrical Performance of Electronic Packaging,.

Measuring the Transmission Characteristic of the Human Body in an Electrostatic-Coupling Intra Body Communication System Using a Square Test Stimulus

Chien-Nan Jimmy Liu, Chauchin Su, Yuhwai Tseng, 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Tree-Topology Multiplexer for Multiphase Clock System

Chien-Nan Jimmy Liu, Chauchin Su, Hungwen Lu, 2009, IEEE Trans. Circuits Syst. I Regul. Pap..

Engineering information abstract (part II)Analog signal metrology for mixed signal ICS

Chauchin Su, Yue-Tsang Chen, Yi-Ren Cheng, 1999 .

Cumulative Differential Nonlinearity Testing of ADCs

Yingchieh Ho, Hungkai Chen, Chauchin Su, 2012, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Hierarchical techniques for symbolic analysis of large electronic circuits

Shyh-Jye Jou, Chauchin Su, Mei-Fang Perng, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

Long-Range Prediction for Real-Time MPEG Video Traffic: An $H_{\infty}$ Filter Approach

Bore-Kuen Lee, Bor-Sen Chen, Chien-Nan Jimmy Liu, 2008, IEEE Transactions on Circuits and Systems for Video Technology.

A parallel event-driven MOS timing simulator on distributed-memory multiprocessors

Shyh-Jye Jou, Chauchin Su, Wen-Hsing Hsieh, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

Decentralized BIST for 1149.1 and 1149.5 based interconnects

Shyh-Jye Jou, Chauchin Su, Yuan-Tzu Ting, 1996, Proceedings ED&TC European Design and Test Conference.

Estimation of Loss Coefficients of Nonlinear Rubber Using Iterative H/spl infin/ Filter

Bore-Kuen Lee, Chauchin Su, Wei-Hang Tseng, 2006, 2006 IEEE International Conference on Systems, Man and Cybernetics.

Intrinsic response for analog module testing using an analog testability bus

Shyh-Jye Jou, Chauchin Su, Yue-Tsang Chen, 2001, TODE.

Structural approach for performance driven ECC circuit synthesis

Shyh-Jye Jou, Chauchin Su, E. Y. Chen, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

Analog metrology and stimulus selection in a noisy environment

Chauchin Su, Yue-Tsang Chen, Chung-Len Lee, 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

All digital built-in delay and crosstalk measurement for on-chip buses

Chauchin Su, Yue-Tsang Chen, Chung-Len Lee, 2000, DATE '00.

Timing Jitter and Modulation Profile Extraction for Spread-Spectrum Clocks

Chauchin Su, Jen-Chien Hsu, 2010, IEEE Transactions on Instrumentation and Measurement.

Comprehensive interconnect BIST methodology for virtual socket interface

Chauchin Su, Yue-Tsung Chen, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

Parallel event-driven MOS timing simulator on distributed memory multiprocessors

Shyh-Jye Jou, Chauchin Su, W.-H. Hsieh, 1996 .

A 0.1–0.3 V 40–123 fJ/bit/ch On-Chip Data Link With ISI-Suppressed Bootstrapped Repeaters

Yingchieh Ho, Chauchin Su, 2012, IEEE Journal of Solid-State Circuits.

Impulse response fault model and fault extraction for functional level analog circuit diagnosis

Shyh-Jye Jou, Chauchin Su, Shenshung Chiang, 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

A computer aided engineering system for memory BIST

Chauchin Su, Chung-Len Lee, Shih-Ching Hsiao, 2001, ASP-DAC '01.

A sub-100µW multi-functional cardiac signal processor for mobile healthcare applications

Ray-Jade Chen, Yingchieh Ho, Chauchin Su, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection

Chauchin Su, Katherine Shu-Min Li, Chung-Len Lee, 2007, J. Electron. Test..

A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus

Chauchin Su, Katherine Shu-Min Li, Chung-Len Lee, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Boundary scan BIST methodology for reconfigurable systems

Chauchin Su, Yue-Tsang Chen, Shung-Won Jeng, 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

A universal BIST methodology for interconnects

Chauchin Su, Chiyuan Chang, 1993, 1993 IEEE International Symposium on Circuits and Systems.

A linear optimal test generation algorithm for interconnect testing

Chauchin Su, 1998, ICCAD '98.

Syndrome simulation and syndrome test for unscanned interconnects

Shyh-Jye Jou, Chauchin Su, Yuan-Tzu Ting, 1996, Proceedings of the Fifth Asian Test Symposium (ATS'96).

High-R Poly Resistance Deviation Improvement From Suppressions of Back-End Mechanical Stresses

Yingchieh Ho, Chauchin Su, Tingyou Lin, 2017, IEEE Transactions on Electron Devices.

All digital built-in delay and crosstalk measurement for on-chip buses

Chauchin Su, Chung-Len Lee, Mu-Jeng Huang, 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).