D. Miles

A high performance 90 nm logic technology with a 37 nm gate length, dual plasma nitrided gate dielectric and differential offset spacer

P. Nicollian, J. Deloach, R. Khamankar, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

Salicides: materials, scaling and manufacturability issues for future integrated circuits

J. Kittl, Q. Hong, W. Shiau, 1999 .

Nickel SALICIDE technology for sub-100nm CMOS devices

D. Mercer, J. P. Lu, Donald S. Miles, 2004 .

Nickel SALICIDE Process Technology for CMOS Devices of 90nm Node and Beyond

Bill Y. Lin, T. Bonifield, F. Johnson, 2006, 2006 International Workshop on Junction Technology.

An enhanced 90nm high performance technology with strong performance improvements from stress and mobility increase through simple process changes

B. Hornung, C. Machala, A. Krishnan, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

A novel nickel SALICIDE process technology for CMOS devices with sub-40 nm physical gate length

J. Zhao, T. Grider, D. Mercer, 2002, Digest. International Electron Devices Meeting,.