E. Torbey

High-level synthesis of digital circuits using genetic algorithms

E. Torbey, J. P. Knight, 1998, 1998 IEEE International Conference on Evolutionary Computation Proceedings. IEEE World Congress on Computational Intelligence (Cat. No.98TH8360).

Performing scheduling and storage optimization simultaneously using genetic algorithms

E. Torbey, J. P. Knight, 1998, 1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268).

Implementation and trade-offs of a DCT architecture using high-level synthesis

E. Torbey, J. P. Knight, 1998, Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372).

Architectural synthesis for digital neural networks

E. Torbey, B. Haroun, 1992, [Proceedings 1992] IJCNN International Joint Conference on Neural Networks.