J. P. Knight

High-level synthesis of digital circuits using genetic algorithms

E. Torbey, J. P. Knight, 1998, 1998 IEEE International Conference on Evolutionary Computation Proceedings. IEEE World Congress on Computational Intelligence (Cat. No.98TH8360).

Performing scheduling and storage optimization simultaneously using genetic algorithms

E. Torbey, J. P. Knight, 1998, 1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268).

'Wireless Bimboards'-the use of programmable gate arrays in a logic design laboratory

J. P. Knight, N. Mikhail, 1990, Proceedings of the 33rd Midwest Symposium on Circuits and Systems.

Implementation and trade-offs of a DCT architecture using high-level synthesis

E. Torbey, J. P. Knight, 1998, Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372).

Control/data flow graph synthesis using evolutionary computation and behavioral estimation

J. P. Knight, Elie Torbey, 1999 .

PASSOS: a different approach for assignment and scheduling for power, area and speed optimization in high-level synthesis

Raul San Martin, J. P. Knight, 1994, Proceedings of 1994 37th Midwest Symposium on Circuits and Systems.

Interactive visualisation of the flight phase of trampoline movements

M. R. Yeadon, J. P. Knight, 2006 .

Methods for computer estimation of word lengths for behaviorally synthesized digital ASICs

J. P. Knight, Y. Kumar, 1991, [1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design.

Reconfigurable logic design case

Calvin Plett, J. P. Knight, Shing-Fat Fred Ma, 2002, SPIE ITCom.

Using Spice and behavioral synthesis tools to optimize ASICs' peak power consumption

J. P. Knight, R. S. Martin, 1995, 38th Midwest Symposium on Circuits and Systems. Proceedings.

Computer-Aided Synthesis of Data-Path by using a Simulated-Annealing-based approach

E. F. Girczyc, A. R. Newton, C. D. Gelatt, 1991 .