Hiroki Shimano

On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform

Kazutami Arimoto, Katsumi Dosaka, Fukashi Morishita, 2009, IEICE Trans. Electron..

Multi-Function Programmable SOI-Memory MFPM

Kazutami Arimoto, Hiroki Shimano, Takashi Fujino, 2010 .

A voltage scalable advanced DFM RAM with accelerated screening for low power SoC platform

Kazutami Arimoto, Katsumi Dosaka, Fukashi Morishita, 2006, 2006 IEEE Asian Solid-State Circuits Conference.

Approaches to extra low voltage DRAM operation by SOI-DRAM

T. Iwamatsu, Narumi Sakashita, Masahide Inuishi, 1998 .

Application of SR lithography to 0.14-um device fabrication

Hiroshi Watanabe, Yasutaka Nishioka, Nobutoshi Mizusawa, 1996, Advanced Lithography.

A built-in self-test circuit with timing margin test function in a 1 Gbit synchronous DRAM

Kazuo Kyuma, Tetsuo Tada, Narumi Sakashita, 1996, Proceedings International Test Conference 1996. Test and Design Validity.

A voltage scalable advanced DFM RAM with accelerated screening for low power SoC platform

Kazutami Arimoto, Fukashi Morishita, Katsumi Dosaka, 2006 .

Design Optimization of Synchrotron Radiation Lithography Beamline for a Compact Storage Ring

Hiroki Shimano, Takashi Hifumi, Yoshihiko Ozaki, 1992 .