Kerry Bernstein

发表

Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks

Aamir Zia, Philip Jacob, Jin Woo Kim, 2009, Proceedings of the IEEE.

High Speed CMOS Design Styles

Christopher M. Durham, Keith M. Carrig, Patrick R. Hansen, 1998 .

Circuit Design Margin and Design Variability

Keith M. Carrig, Christopher M. Durham, Patrick R. Hansen, 1999 .

Ultralow-voltage, minimum-energy CMOS

David Blaauw, Bo Zhai, Dennis Sylvester, 2006, IBM J. Res. Dev..

Design and CAD Challenges in sub-90nm CMOS Technologies

Rajiv V. Joshi, Ching-Te Chuang, Ruchir Puri, 2003, ICCAD.

Practical performance/power alternatives within an existing CMOS technology generation

Edward J. Nowak, William F. Clark, Kerry Bernstein, 1996, ISLPED '96.

Reshaping EDA for power

David Blaauw, Jan M. Rabaey, Wolfgang Nebel, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

Three-dimensional integrated circuits

Arvind Kumar, Steven E. Steen, Anna W. Topol, 2006, IBM J. Res. Dev..

High Performance CMOS Variability in the 65nm Regime and Beyond

Sani R. Nassif, David J. Frank, D. J. Pearson, 2007 .

F1: Silicon 3D-integration technology and systems

Vladimir Stojanovic, Hideto Hidaka, Ken Takeuchi, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

SOI circuit design concepts

Norman J. Rohrer, Kerry Bernstein, K. Bernstein, 2000 .

Device and Architecture Outlook for Beyond CMOS Switches

Wolfgang Porod, Ralph K. Cavin, Kerry Bernstein, 2010, Proceedings of the IEEE.

Murphy was an optimist: Embracing asymmetry in electronics

Kerry Bernstein, 2018, ISQED.

High Performance CMOS Variability in the 65nm Regime and Beyond

Sani R. Nassif, Edward J. Nowak, Wilfried Haensch, 2006, 2007 IEEE International Electron Devices Meeting.

Microarchitecture on the MOSFET diet

Kerry Bernstein, 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

Tutorial Part 1: Nanometer-Scale CMOS Devices

Kerry Bernstein, 2004 .

Dependability analysis of nano-scale FinFET circuits

Yuan Xie, Yan Luo, Feng Wang, 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

Interconnects in the Third Dimension: Design Challenges for 3D ICs

Philip G. Emma, Mike Ignatowski, Wilfried Haensch, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Analysis of the effect of the gate oxide breakdown on SRAM stability

Rajiv V. Joshi, Barry P. Linder, Gregory A. Northrop, 2002, Microelectron. Reliab..

Microarchitecture on the MOSFET Diet

Kerry Bernstein, 2003, MICRO.

Experimental 2.0 V power/performance optimization of a 3.6 V-design CMOS microprocessor-PowerPC 601

Francis Roger White, Kerry Bernstein, Edward J. Nowak, 1994, Proceedings of 1994 VLSI Technology Symposium.

F1: Designing secure systems: Manufacturing, circuits and architectures

Marian Verhelst, Yusuf Leblebici, Vivek De, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

"Out-of-the-park home runs" - legendary digital circuits that tracked technology scaling

Kerry Bernstein, 2007, IEEE Solid-State Circuits Newsletter.

Design and CAD Challenges in sub-90nm CMOS Technologies

Ching-Te Chuang, Ruchir Puri, Kerry Bernstein, 2003, ICCAD 2003.

Reduced-voltage power/performance optimization of the 3.6-volt PowerPC 601 Microprocessor

Edward J. Nowak, Kerry Bernstein, John E. Bertsch, 1995, IBM J. Res. Dev..

Three dimensional CMOS devices and integrated circuits

Rajiv V. Joshi, J. Kedzierski, Meikei Ieong, 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

Nanometer-scale CMOS devices

Kerry Bernstein, 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

The Impact of Width Granularity on FinFET Latch Operation and Optimization

Huifang Qin, Thomas Ludwig, Jan Rabaey, 2004 .

New Dimension in Performance: Harnessing 3D Integration Technology

Kerry Bernstein, 2007 .