K. K. Parhi

Pipelining of orthogonal double-rotation digital lattice filters

K. Parhi, Jin-Gyun Chung, K. K. Parhi, 1993, Proceedings of 27th Asilomar Conference on Signals, Systems and Computers.

Look-ahead in dynamic programming and quantizer loops

Keshab K. Parhi, K. K. Parhi, 1989, IEEE International Symposium on Circuits and Systems,.

Generalized ILP scheduling and allocation for high-level DSP synthesis

Keshab K. Parhi, L. E. Lucke, K. K. Parhi, 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

High level DSP synthesis using the MARS design system

Keshab K. Parhi, C.-Y. Wang, K. K. Parhi, 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

Systematic design approach of Mastrovito multipliers over GF(2/sup m/)

Keshab K. Parhi, Tong Zhang, Tong Zhang, 2000, 2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528).

A high-speed CORDIC algorithm and architecture for DSP applications

Keshab K. Parhi, Martin Kuhlmann, K. K. Parhi, 1999, 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461).

Low-power digit-serial multipliers

Keshab K. Parhi, Yun-Nan Chang, J. H. Satyanarayana, 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

A 54 Mbps (3,6)-regular FPGA LDPC decoder

Keshab K. Parhi, Tong Zhang, Tong Zhang, 2002, IEEE Workshop on Signal Processing Systems.