Charlie Brej

发表

Self-timed full adder designs based on hybrid input encoding

P. Balasubramanian, David A. Edwards, Charlie Brej, 2009, 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Wagging Logic: Implicit Parallelism Extraction Using Asynchronous Methodologies

Charlie Brej, 2010, 2010 10th International Conference on Application of Concurrency to System Design.

A quasi-delay-insensitive method to overcome transistor variation

Jim D. Garside, Charlie Brej, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Forward and backward guarding in early output logic

Doug Edwards, Charlie Brej, D. Edwards, 2009, 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.