V. Vashishtha

ASAP5: A predictive PDK for the 5 nm node

L. Clark, V. Vashishtha, 2022, Microelectronics Journal.

Design flows and collateral for the ASAP7 7nm FinFET predictive process design kit

Lawrence T. Clark, David M. Harris, Vinay Vashishtha, 2017, 2017 IEEE International Conference on Microelectronic Systems Education (MSE).

ASAP7: A 7-nm finFET predictive process design kit

Saurabh Sinha, Brian Cline, Greg Yeric, 2016, Microelectron. J..

Comparing bulk-Si FinFET and gate-all-around FETs for the 5 ​nm technology node

Lawrence T. Clark, Vinay Vashishtha, L. Clark, 2021, Microelectron. J..

Muller C-element Self-corrected Triple Modular Redundant Logic with Multithreading and Low Power Modes

L. T. Clark, C. Ramamurthy, A. Gujja, 2017, 2017 17th European Conference on Radiation and Its Effects on Components and Systems (RADECS).

Advanced encryption system with dynamic pipeline reconfiguration for minimum energy operation

Srivatsan Chellappa, Lawrence T. Clark, Chandarasekaran Ramamurthy, 2015, Sixteenth International Symposium on Quality Electronic Design.

ASAP7 predictive design kit development and cell design technology co-optimization: Invited paper

Lawrence T. Clark, Vinay Vashishtha, Manoj Vangala, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).