Gabriel H. Loh

发表

A Comparison of Asymptotically Scalable Superscalar Processors

Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh, 2001, Theory of Computing Systems.

Challenges of High-Capacity DRAM Stacks and Potential Directions

Gabriel H. Loh, Amin Farmahini Farahani, Sudhanva Gurumurthi, 2018, MCHPC@SC.

Applying Machine Learning for Ensemble Branch Predictors

Dana S. Henry, Gabriel H. Loh, 2002, IEA/AIE.

Thermal analysis of a 3D die-stacked high-performance microprocessor

Gabriel H. Loh, Kiran Puttaswamy, Kiran Puttaswamy, 2006, GLSVLSI '06.

Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap

Mark D. Hill, Gabriel H. Loh, M. Hill, 2012, IEEE Micro.

A case for hierarchical rings with deflection routing: An energy-efficient on-chip communication substrate

Reetuparna Das, Kevin Kai-Wei Chang, Rachata Ausavarungnirun, 2016, Parallel Comput..

Microarchitectural Floorplanning Under Performance and Thermal Tradeoff

Hsien-Hsin S. Lee, Sung Kyu Lim, Gabriel H. Loh, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Design and Analysis of an APU for Exascale Computing

Matthew Poremba, Indrani Paul, Wei Huang, 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).

A register-file approach for row buffer caches in die-stacked DRAMs

Gabriel H. Loh, 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Use ECP, not ECC, for hard failures in resistive memories

Karin Strauss, Gabriel H. Loh, Stuart E. Schechter, 2010, ISCA.

Design and Evaluation of Hierarchical Rings with Deflection Routing

Reetuparna Das, Kevin Kai-Wei Chang, Rachata Ausavarungnirun, 2014, 2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing.

Static strands: Safely exposing dependence chains for increasing embedded power efficiency

Gabriel H. Loh, Peter G. Sassone, D. Scott Wills, 2007, TECS.

HpMC: An Energy-aware Management System of Multi-level Memory Architectures

Bronis R. de Supinski, Kirk W. Cameron, Chun-Yi Su, 2015, MEMSYS.

Die Stacking (3D) Microarchitecture

Lei Jiang, John Paul Shen, Gabriel H. Loh, 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories

David Roberts, Gabriel H. Loh, Mike Ignatowski, 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).

Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems

Kevin Kai-Wei Chang, Rachata Ausavarungnirun, Onur Mutlu, 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).

Computer architecture for die stacking

Gabriel H. Loh, 2012, Proceedings of Technical Program of 2012 VLSI Technology, System and Application.

Speculative Clustered Caches for Clustered Processors

Dana S. Henry, Gabriel H. Loh, Rahul Sami, 2002, ISHPC.

Modular Routing Design for Chiplet-Based Systems

Natalie D. Enright Jerger, Matthew Poremba, Gabriel H. Loh, 2018, 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA).

GPU System Calls pdf

Ján Veselý, Mark Oskin, Gabriel H. Loh, 2017, ArXiv.

Static strands: safely collapsing dependence chains for increasing embedded power efficiency

Gabriel H. Loh, Peter G. Sassone, D. Scott Wills, 2005, LCTES '05.

Design and optimization of the store vectors memory dependence predictor

Gabriel H. Loh, Samantika Subramaniam, Samantika Subramaniam, 2009, TACO.

Efficient shared cache management for multicore processors

Gabriel H. Loh, Yuejian Xie, 2011 .

μC-States: Fine-grained GPU datapath power management

Mahmut T. Kandemir, Chita R. Das, Rachata Ausavarungnirun, 2016, 2016 International Conference on Parallel Architecture and Compilation Techniques (PACT).

Thread-aware dynamic shared cache compression in multi-core processors

Gabriel H. Loh, Yuejian Xie, 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

3D-Stacked Memory Architectures for Multi-core Processors

Gabriel H. Loh, G. Loh, 2008, 2008 International Symposium on Computer Architecture.

Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs

Sung Kyu Lim, Gabriel H. Loh, Mongkol Ekpanyapong, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories

Dean M. Tullsen, Gabriel H. Loh, Mitesh R. Meswani, 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Exploiting data-width locality to increase superscalar execution bandwidth

Gabriel H. Loh, 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..

Guest Editorial

Yuan Xie, Gabriel H. Loh, Yuan Xie, 2013, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Last-level cache deduplication

Samira Manabi Khan, Daniel A. Jiménez, Gabriel H. Loh, 2014, ICS '14.

Invited: Efficient System Architecture in the Era of Monolithic 3D: Dynamic Inter-Tier Interconnect and Processing-in-Memory

Yuan Xie, Gabriel H. Loh, Wenqin Huangfu, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Proceedings of the 46th International Symposium on Computer Architecture

Sang Lyul Min, Gabriel H. Loh, 2019, ISCA.

Fire-and-Forget: Load/Store Scheduling with No Store Queue at All

Gabriel H. Loh, Samantika Subramaniam, Samantika Subramaniam, 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor

Tao Zhang, Yuan Xie, Zhe Wang, 2016, 2016 28th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD).

A Time Stamping Algorithm for Computing the Critical Path of Program Execution on Superscalar Processors

Gabriel H. Loh, 2000 .

Scalable Shared-Cache Management by Containing Thrashing Workloads

Gabriel H. Loh, Yuejian Xie, 2010, HiPEAC.

Implementing register files for high-performance microprocessors in a die-stacked (3D) technology

Gabriel H. Loh, Kiran Puttaswamy, 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

Quantifying and coping with parametric variations in 3D-stacked microarchitectures

Alok N. Choudhary, Abhishek Das, Gabriel H. Loh, 2010, Design Automation Conference.

Matrix scheduler reloaded

Gabriel H. Loh, Peter G. Sassone, Bryan Black, 2007, ISCA '07.

Optimizing GPU energy efficiency with 3D die-stacking graphics memory and reconfigurable memory interface

Yuan Xie, Jishen Zhao, Gabriel H. Loh, 2013, TACO.

A comparison of scalable superscalar processors

Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh, 1999, SPAA '99.

Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache

Babak Falsafi, Gabriel H. Loh, Djordje Jevdjic, 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

Hyesoon Kim, Alaa R. Alameldeen, Chris Wilkerson, 2014 .

Cost-effective design of scalable high-performance systems using active and passive interposers

Yuan Xie, Gabriel H. Loh, Dylan Stow, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

CAREER: Computer architecture foundations for 3D-integrated high-performance microprocessors

Gabriel H. Loh, 2011 .

Using TLB Speculation to Overcome Page Splintering in Virtual Machines

Gabriel H. Loh, Abhishek Bhattacharjee, Jan Vesely, 2015 .

Exploiting Bias in the Hysteresis Bit of 2-bit Saturating Counters in Branch Predictors

Arvind Krishnamurthy, Dana S. Henry, Gabriel H. Loh, 2003, J. Instr. Level Parallelism.

Store vectors for scalable memory dependence prediction and scheduling

Gabriel H. Loh, Samantika Subramaniam, Samantika Subramaniam, 2006, The Twelfth International Symposium on High-Performance Computer Architecture, 2006..

Dynamic instruction schedulers in a 3-dimensional integration technology

Gabriel H. Loh, Kiran Puttaswamy, Kiran Puttaswamy, 2006, GLSVLSI '06.

Improving processor efficiency by exploiting common-case behaviors of memory instructions

Gabriel H. Loh, Samantika Subramaniam, Samantika Subramaniam, 2009 .

Machine Learning for Performance and Power Modeling of Heterogeneous Systems

Gabriel H. Loh, Joseph L. Greathouse, J. Greathouse, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Deconstructing the Inefficacy of Global Cache Replacement Policies

Gabriel H. Loh, Samantika Subramaniam, Rahul V. Garde, 2008 .

Zesto: A cycle-level simulator for highly detailed microarchitecture exploration

Gabriel H. Loh, Yuejian Xie, Samantika Subramaniam, 2009, 2009 IEEE International Symposium on Performance Analysis of Systems and Software.

A simple divide-and-conquer approach for neural-class branch prediction

Gabriel H. Loh, 2005, 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05).

Static strands: safely collapsing dependence chains for increasing embedded power efficiency

Gabriel H. Loh, Peter G. Sassone, D. Scott Wills, 2005, LCTES.

There and back again: Optimizing the interconnect in networks of memory cubes

Matthew Poremba, Yuan Xie, Gabriel H. Loh, 2017, 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA).

The impact of 3-dimensional integration on the design of arithmetic units

Gabriel H. Loh, Kiran Puttaswamy, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Deconstructing the Frankenpredictor for Implementable Branch Predictors

Gabriel H. Loh, 2005, J. Instr. Level Parallelism.

Avoiding TLB Shootdowns Through Self-Invalidating TLB Entries

Yan Solihin, Gabriel H. Loh, Amro Awad, 2017, 2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT).

Observations and opportunities in architecting shared virtual memory for heterogeneous systems

Ján Veselý, Mark Oskin, Gabriel H. Loh, 2016, 2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

Implementing caches in a 3D technology for high performance processors

Gabriel H. Loh, Kiran Puttaswamy, Kiran Puttaswamy, 2005, 2005 International Conference on Computer Design.

Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors

Gabriel H. Loh, Kiran Puttaswamy, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Entropy-based low power data TLB design

Gabriel H. Loh, Chinnakrishnan S. Ballapuram, Kiran Puttaswamy, 2006, CASES '06.

Exploiting data-width locality to increase superscalar execution bandwidth

Gabriel H. Loh, 2002, MICRO 35.

Double-DIP: Augmenting DIP with Adaptive Promotion Policies to Manage Shared L2 Caches

Gabriel H. Loh, Jonathan D. Kron, Brooks Prumo, 2008 .

Width-Partitioned Load Value Predictors

Gabriel H. Loh, 2003, J. Instr. Level Parallelism.

OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures

Chita R. Das, Yuan Xie, Gabriel H. Loh, 2016, 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

2014 Hardware-Software Co-Design for High Performance Computing Co-HPC 2014 Table of Contents

Gabriel H. Loh, Mike Ignatowski, Mitesh R. Meswani, 2014 .

PEEP: Exploiting predictability of memory dependences in SMT processors

Milos Prvulovic, Gabriel H. Loh, Samantika Subramaniam, 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

Toward Efficient Programmer-Managed Two-Level Memory Hierarchies in Exascale Computers

David Roberts, Gabriel H. Loh, Mike Ignatowski, 2014, 2014 Hardware-Software Co-Design for High Performance Computing.

Three-Dimensional Microprocessor Design

Gabriel H. Loh, 2010 .

3D-Integrated SRAM Components for High-Performance Microprocessors

Gabriel H. Loh, Kiran Puttaswamy, Kiran Puttaswamy, 2009, IEEE Transactions on Computers.

Interconnect-Memory Challenges for Multi-chip, Silicon Interposer Systems

Natalie D. Enright Jerger, Gabriel H. Loh, Yasuko Eckert, 2015, MEMSYS.

Achieving Exascale Capabilities through Heterogeneous Computing

Indrani Paul, Gabriel H. Loh, Sudhanva Gurumurthi, 2015, IEEE Micro.

Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance

Mahmut T. Kandemir, Chita R. Das, Rachata Ausavarungnirun, 2015, 2015 International Conference on Parallel Architecture and Compilation (PACT).

Exploiting New Interconnect Technologies in On-Chip Communication

Kiyoung Choi, John Kim, Gabriel H. Loh, 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Preventing PCM banks from seizing too much power

Karin Strauss, Gabriel H. Loh, Timothy Sherwood, 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Adaptive Caches: Effective Shaping of Cache Behavior to Workloads

Yannis Smaragdakis, Gabriel H. Loh, Ranjith Subramanian, 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

Efficient synthetic traffic models for large, complex SoCs

Natalie D. Enright Jerger, Matthew Poremba, Gabriel H. Loh, 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).

High-Performance and Energy-Effcient Memory Scheduler Design for Heterogeneous Systems pdf

Rachata Ausavarungnirun, Onur Mutlu, Gabriel H. Loh, 2018, ArXiv.

Simulation Differences Between Academia and Industry: A Branch Prediction Case Study

Gabriel H. Loh, 2005, IEEE International Symposium on Performance Analysis of Systems and Software, 2005. ISPASS 2005..

Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy

Gabriel H. Loh, G. Loh, 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors

Gabriel H. Loh, Kiran Puttaswamy, 2007, 2007 IEEE 13th International Symposium on High Performance Computer Architecture.

Achieving both High Energy Efficiency and High Performance in On-Chip Communication using Hierarchical Rings with Deflection Routing pdf

Reetuparna Das, Kevin Kai-Wei Chang, Rachata Ausavarungnirun, 2016, ArXiv.

Top Picks from the 2012 Computer Architecture Conferences

Babak Falsafi, Gabriel H. Loh, 2013, IEEE Micro.

A time-stamping algorithm for efficient performance estimation of superscalar processors

Gabriel H. Loh, 2001, SIGMETRICS '01.

Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory)

Hsien-Hsin S. Lee, Xin Zhao, Sung Kyu Lim, 2015, IEEE Transactions on Computers.

Economic mechanisms for dynamic resource partitioning in multi-core process

Gabriel H. Loh, 2010 .

NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free?

Natalie D. Enright Jerger, Gabriel H. Loh, Zimo Li, 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.

A Software-Managed Approach to Die-Stacked DRAM

Mark Oskin, Gabriel H. Loh, M. Oskin, 2015, 2015 International Conference on Parallel Architecture and Compilation (PACT).

Processor Design in 3D Die-Stacking Technologies

Yuan Xie, Gabriel H. Loh, Bryan Black, 2007, IEEE Micro.

Leveraging near data processing for high-performance checkpoint/restart

Gabriel H. Loh, James Tuck, Abhinav Agrawal, 2017, SC.

Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory

Hsien-Hsin S. Lee, Xin Zhao, Sung Kyu Lim, 2010, IEEE Custom Integrated Circuits Conference 2010.

Thermal optimization in multi-granularity multi-core floorplanning

Hsien-Hsin S. Lee, Sung Kyu Lim, Gabriel H. Loh, 2009, 2009 Asia and South Pacific Design Automation Conference.

A Segmented Bloom Filter Algorithm for Efficient Predictors

Gabriel H. Loh, Peter G. Sassone, Bryan Black, 2008, 2008 20th International Symposium on Computer Architecture and High Performance Computing.

GPU System Call

Mark Oskin, Gabriel H. Loh, Steven K. Reinhardt, 2017 .

Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design

Gabriel H. Loh, Moinuddin K. Qureshi, G. Loh, 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

Scheduling Page Table Walks for Irregular GPU Applications

Yan Solihin, Mark Oskin, Gabriel H. Loh, 2018, 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA).

PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches

Gabriel H. Loh, Yuejian Xie, Yuejian Xie, 2009, ISCA '09.

Architectural Vulnerability Modeling and Analysis of Integrated Graphics Processors

Gabriel H. Loh, Hyeran Jeon, Vilas Sridharan, 2013 .

CODA

Ramyad Hadidi, Gabriel H. Loh, Hyojong Kim, 2017, ACM Trans. Archit. Code Optim..

Enabling interposer-based disintegration of multi-core processors

Natalie D. Enright Jerger, Gabriel H. Loh, Ajaykumar Kannan, 2015, 2015 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

3D-MAPS: 3D Massively parallel processor with stacked memory

Hsien-Hsin S. Lee, Xin Zhao, Sung Kyu Lim, 2012, 2012 IEEE International Solid-State Circuits Conference.

Energy-efficient GPU design with reconfigurable in-package graphics memory

Yuan Xie, Jishen Zhao, Gabriel H. Loh, 2012, ISLPED '12.

Thermal-aware 3D Microarchitectural Floorplanning

Hsien-Hsin S. Lee, Sung Kyu Lim, Gabriel H. Loh, 2004 .

Efficient RAS support for die-stacked DRAM

Gabriel H. Loh, Hyeran Jeon, Murali Annavaram, 2014, 2014 International Test Conference.

A modular 3d processor for flexible product design and technology migration

Gabriel H. Loh, 2008, CF '08.

A Configurable and Strong RAS Solution for Die-Stacked DRAM Caches

Gabriel H. Loh, Vilas Sridharan, Mike O'Connor, 2014, IEEE Micro.

Criticality-based optimizations for efficient load processing

Gabriel H. Loh, Hong Wang, Anne Bracy, 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

Circuits for wide-window superscalar processors

Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh, 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

Resilient die-stacked DRAM caches

Gabriel H. Loh, Vilas Sridharan, Mike O'Connor, 2013, ISCA.

Managing GPU Concurrency in Heterogeneous Architectures

Mahmut T. Kandemir, Chita R. Das, Nachiappan Chidambaram Nachiappan, 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.

Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors

Daniel A. Jiménez, Gabriel H. Loh, 2007, International Journal of Parallel Programming.

Analyzing and Leveraging Shared L1 Caches in GPUs

Gabriel H. Loh, Adwait Jog, Yasuko Eckert, 2020, PACT.

Predicting conditional branches with fusion-based hybrid predictors

Dana S. Henry, Gabriel H. Loh, 2002, Proceedings.International Conference on Parallel Architectures and Compilation Techniques.

Guest Editorial New Interconnect Technologies in On-Chip Communication

Kiyoung Choi, John Kim, Gabriel H. Loh, 2012, IEEE J. Emerg. Sel. Topics Circuits Syst..

Holistic Management of the GPGPU Memory Hierarchy to Manage Warp-level Latency Tolerance pdf

Mahmut T. Kandemir, Chita R. Das, Rachata Ausavarungnirun, 2018, ArXiv.

Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors

Daniel A. Jiménez, Gabriel H. Loh, 2006, 2006 18th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'06).

Intelligent Cache Management by Exploiting Dynamic UTI/MTI Behavior

Hsien-Hsin S. Lee, Gabriel H. Loh, Chad Huneycutt, 2005 .

Memory Bypassing: Not Worth the Effort

Gabriel H. Loh, Daniel H. Friendly, Rahul Sami, 2002 .

Efficiently enabling conventional block sizes for very large die-stacked DRAM caches

Mark D. Hill, Gabriel H. Loh, M. Hill, 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Generic System Calls for GPUs

Ján Veselý, Mark Oskin, Gabriel H. Loh, 2018, 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA).

Revisiting the performance impact of branch predictor latencies

Gabriel H. Loh, 2006, 2006 IEEE International Symposium on Performance Analysis of Systems and Software.

Large pages and lightweight memory management in virtualized environments: Can you have it both ways?

Ján Veselý, Gabriel H. Loh, Abhishek Bhattacharjee, 2015, 2015 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Increasing TLB reach by exploiting clustering in page translations

Gabriel H. Loh, Abhishek Bhattacharjee, Yasuko Eckert, 2014, 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA).

A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch

Gabriel H. Loh, Hyesoon Kim, Mithuna Thottethodi, 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

Managing DRAM Latency Divergence in Irregular GPGPU Applications

Rajeev Balasubramonian, Gabriel H. Loh, Niladrish Chatterjee, 2014, SC14: International Conference for High Performance Computing, Networking, Storage and Analysis.

Intel Corporation

Yuan Xie, Gabriel H. Loh, Bryan Black, 2005 .

Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism pdf

Kevin Kai-Wei Chang, Onur Mutlu, Gabriel H. Loh, 2016, ArXiv.

Experiences with ML-Driven Design: A NoC Case Study

Natalie D. Enright Jerger, Mark Oskin, Gabriel H. Loh, 2020, 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Analyzing and Leveraging Decoupled L1 Caches in GPUs

Gabriel H. Loh, Adwait Jog, Yasuko Eckert, 2021, 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA).

Understanding Chiplets Today to Anticipate Future Integration Opportunities and Limits

Gabriel H. Loh, Samuel Naffziger, Kevin Lepak, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A New Era of Tailored Computing

Gabriel H. Loh, Samuel Naffziger, Mark Papermaster, 2021, 2021 Symposium on VLSI Circuits.