Sanu K. Mathew

发表

A 4 GHz 130 nm address generation unit with 32-bit sparse-tree adder core

Ram Krishnamurthy, Shekhar Borkar, Sanu K. Mathew, 2002, VLSIC 2002.

A 9.0-TOPS/W Hash-Based Deep Neural Network Accelerator Enabling 128× Model Compression in 10-nm FinFET CMOS

Himanshu Kaul, Amit Agarwal, Gregory K. Chen, 2020, IEEE Solid-State Circuits Letters.

High-Performance Energy-Efficient Dual-Supply ALU Design

Ram Krishnamurthy, Sanu K. Mathew, Mark A. Anders, 2006 .

SCHÉMA DE SYNCHRONISATION À BASE DE VERROUILLAGE TRIPHASÉ À FAIBLE ÉNERGIE D'HORLOGE

Vikram B. Suresh, Sanu K. Mathew, Sudhir Satpathy, 2018 .

Enhanced Power and Electromagnetic SCA Resistance of Encryption Engines via a Security-Aware Integrated All-Digital LDO

Vivek De, Saibal Mukhopadhyay, Monodeep Kar, 2020, IEEE Journal of Solid-State Circuits.

A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme

Atila Alvandpour, Shih-Lien Lu, Ram Krishnamurthy, 2003 .

5-GHz 32-bit Integer Execution Core in 130-nm Dual-VT CMOS

Mircea R. Stan, Sriram R. Vangal, Vasantha Erraguntla, 2001 .

Reducing Power Side-Channel Information Leakage of AES Engines Using Fully Integrated Inductive Voltage Regulator

Monodeep Kar, Saibal Mukhopadhyay, Arvind Singh, 2018, IEEE Journal of Solid-State Circuits.

25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range

Vikram Suresh, Himanshu Kaul, Amit Agarwal, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A Digital Low-Dropout Regulator With Autotuned PID Compensator and Dynamic Gain Control for Improved Transient Performance Under Process Variations and Aging

Vivek De, Saibal Mukhopadhyay, Monodeep Kar, 2020, IEEE Transactions on Power Electronics.

Design & Scaling Trends

Ram Krishnamurthy, Krishnamurthy Soumyanath, Kaizad Mistry, 2001 .

A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS

Sudhir Satpathy, Vikram Suresh, Himanshu Kaul, 2017, IEEE Journal of Solid-State Circuits.

High–performance, low–power, and leakage–tolerance challenges for sub–70nm microprocessor circuits

Atila Alvandpour, Vivek De, Ram Krishnamurthy, 2002 .

$\mu $ RNG: A 300–950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS

Vikram Suresh, Himanshu Kaul, Amit Agarwal, 2016, IEEE Journal of Solid-State Circuits.

Advanced circuit techniques for high-performance microprocessor design challenges

Sanu K. Mathew, 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

Improved Power/EM Side-Channel Attack Resistance of 128-Bit AES Engines With Random Fast Voltage Dithering

Monodeep Kar, Saibal Mukhopadhyay, Arvind Singh, 2019, IEEE Journal of Solid-State Circuits.

A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition

Sudhir Satpathy, Vikram Suresh, Himanshu Kaul, 2020, IEEE Journal of Solid-State Circuits.

16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS

Himanshu Kaul, Amit Agarwal, Shekhar Borkar, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

Instruction-Scheduler Loop

Krishnamurthy Soumyanath, Ram Krishnamurthy, Shekhar Borkar, 2002 .

An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS

Vikram Suresh, Himanshu Kaul, Amit Agarwal, 2019, IEEE Journal of Solid-State Circuits.

90nm Dual VT CMOS

Sriram R. Vangal, Vasantha Erraguntla, Nitin Borkar, 2003 .

16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS

Himanshu Kaul, Amit Agarwal, Gregory K. Chen, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors

Himanshu Kaul, Amit Agarwal, Ram Krishnamurthy, 2012, IEEE Journal of Solid-State Circuits.

Advanced high-performance microprocessor design challenges and solutions

Atila Alvandpour, Sanu K. Mathew, 2002, 15th Annual IEEE International ASIC/SOC Conference.

A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS

Sudhir Satpathy, Vikram Suresh, Himanshu Kaul, 2021, IEEE Journal of Solid-State Circuits.

A Skein-512 Hardware Implementation

Ram Krishnamurthy, Farhana Sheikh, Sanu K. Mathew, 2010 .

Sub-500-ps 64-b ALUs in 0 . 18-m SOI / Bulk CMOS : Design and Scaling Trends

K. Soumyanath, Sanu K. Mathew, Mark A. Anders, 2001 .