M. Ostermayr

A 1 Mbit SRAM test structure to analyze local mismatch beyond 5 sigma variation

D. Schmitt-Landsiedel, T. Fischer, C. Otte, 2007, 2007 IEEE International Conference on Microelectronic Test Structures.

MALTY--A memory test structure for analysis in the early phase of the technology development

Th. Nirschl, M. Omer, M. Ostermayr, 2003, Microelectron. Reliab..

Competitive and cost effective high-k based 28nm CMOS technology for low power applications

J. Bonnouvrier, R. Augur, F. Arnaud, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Investigation of Increased Multi-Bit Failure Rate Due to Neutron Induced SEU in Advanced Embedded SRAMs

E. Amirante, M. Ostermayr, P. Huber, 2007, 2007 IEEE Symposium on VLSI Circuits.

Analysis of Read Current and Write Trip Voltage Variability From a 1-MB SRAM Test Structure

D. Schmitt-Landsiedel, E. Amirante, A. Olbrich, 2008, IEEE Transactions on Semiconductor Manufacturing.

High-κ/metal gate low power bulk technology - Performance evaluation of standard CMOS logic circuits, microprocessor critical path replicas, and SRAM for 45nm and beyond

C. Pacha, M. Sherony, A. Steegen, 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

A 65nm test structure for the analysis of NBTI induced statistical variation in SRAM transistors

D. Schmitt-Landsiedel, K. Hofmann, M. Ostermayr, 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.

The tunneling field effect transistor (TFET) as an add-on for ultra-low-voltage analog and digital processes

D. Schmitt-Landsiedel, C. Pacha, W. Hansch, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..