G. Ellguth

The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing pdf

Jim D. Garside, Steve B. Furber, Johannes Partzsch, 2021, ArXiv.

The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing

S. Furber, C. Mayr, J. Garside, 2021, ArXiv.

Dynamic voltage and frequency scaling for neuromorphic many-core systems

Jim D. Garside, Steve B. Furber, Luis A. Plana, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

A 32 GBit/s communication SoC for a waferscale neuromorphic system

Stephan Henker, René Schüffny, Johannes Partzsch, 2012, Integr..

A Biological-Realtime Neuromorphic System in 28 nm CMOS Using Low-Leakage Switched Capacitor Circuits

René Schüffny, Marko Noack, Johannes Partzsch, 2014, IEEE Transactions on Biomedical Circuits and Systems.

Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS

René Schüffny, Marko Noack, Johannes Partzsch, 2014, Front. Neurosci..

A database accelerator for energy-efficient query processing and optimization

Wolfgang Lehner, Gerhard P. Fettweis, René Schüffny, 2016, 2016 IEEE Nordic Circuits and Systems Conference (NORCAS).

Dynamic Power Management for Neuromorphic Many-Core Systems

Steve Furber, Luis A. Plana, Johannes Partzsch, 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 12-b 4-MS/s SAR ADC With Configurable Redundancy in 28-nm CMOS Technology

René Schüffny, Sebastian Höppner, Stefan Hänzsche, 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 16-Channel Fully Configurable Neural SoC With 1.52 $\mu$W/Ch Signal Acquisition, 2.79 $\mu$W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI

Franz Marcus Schüffny, C. Mayr, D. Walter, 2022, IEEE Transactions on Biomedical Circuits and Systems.