M. Jurczak

发表

Comparison of scaled floating body RAM architectures

R. Rooyackers, L. Witters, N. Collaert, 2008, 2008 IEEE International SOI Conference.

Gate length impact on UTBOX FBRAM devices

E. Simoen, C. Claeys, A. Veloso, 2012, 2012 IEEE International SOI Conference (SOI).

Reliability study in capacitor less 1T-RAM cells on SOI

A. Mercha, E. Simoen, N. Collaert, 2010, 2010 IEEE International SOI Conference (SOI).

Modeling RRAM set/reset statistics resulting in guidelines for optimized operation

G. Groeseneken, R. Degraeve, L. Goux, 2013, 2013 Symposium on VLSI Technology.

Linear SVM for organizing data

M. Jurczak, M. Jurczak, 2006 .

Origin of wide retention distribution in 1T Floating Body RAM

G. Groeseneken, E. Simoen, C. Claeys, 2012, 2012 IEEE International SOI Conference (SOI).

Low-frequency noise of advanced memory devices

E. Simoen, C. Claeys, R. Ritzenthaler, 2015, 2015 International Conference on Noise and Fluctuations (ICNF).

Quantitative model for post-program instabilities in filamentary RRAM

R. Degraeve, L. Goux, B. Govoreanu, 2016, 2016 IEEE International Reliability Physics Symposium (IRPS).

Design-driven optimisation of a 90 nm RF CMOS process by use of elevated source/drain

P. Wambacq, S. Decoutere, V. Vassilev, 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..

Impact of elevated source drain architecture on ESD protection devices for a 90nm CMOS technology node

R. Rooyackers, G. Groeseneken, V. Vassilev, 2003, 2003 Electrical Overstress/Electrostatic Discharge Symposium.

First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling

R. Rooyackers, B. Duriez, G. Curatola, 2008, 2008 IEEE International Electron Devices Meeting.

Design methodology of FinFET devices that meet IC-Level HBM ESD targets

R. Rooyackers, G. Groeseneken, M. Sawada, 2008, EOS/ESD 2008 - 2008 30th Electrical Overstress/Electrostatic Discharge Symposium.

Junction Field Effect on the Retention Time for One-Transistor Floating-Body RAM

G. Groeseneken, E. Simoen, P. Blomme, 2012, IEEE Transactions on Electron Devices.

ESD protection for sub-45 nm MugFET technology

N. Collaert, D. Linten, G. Groeseneken, 2007, 2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Structure of interlocking table

M. Jurczak, 2011 .

Intrinsic program instability in HfO2 RRAM and consequences on program algorithms

A. Cabrini, G. Torelli, R. Degraeve, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

The Dependence of Retention Time on Gate Length in UTBOX FBRAM With Different Source/Drain Junction Engineering

E. Simoen, C. Claeys, A. Veloso, 2012, IEEE Electron Device Letters.

Complexity control of SVM network applied to text categorisation

M. Jurczak, 2004 .

Towards optimally shaped fins in p-channel tri-gate FETs: can fin height be reduced further?

R. Rooyackers, A. Mercha, N. Collaert, 2005, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..

Logistyczne nowosci na Pakfood 2009

M. Jurczak, 2009 .

Quantitative endurance failure model for filamentary RRAM

R. Degraeve, L. Goux, B. Govoreanu, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Analysis of the FinFET parasitics for improved RF performances

B. Parvais, A. Mercha, S. Decoutere, 2007, 2007 IEEE International SOI Conference.

Suitability ofFinFETtechnology forlow-power mixed-signal applications

P. Wambacq, Rita Rooyackers, S. Decoutere, 2006 .

Influence of changing station layout over railway interlocking

M. Jurczak, 2012 .

Suitability of FinFET technology for low-power mixed-signal applications

P. Wambacq, B. Parvais, R. Rooyackers, 2006, 2006 IEEE International Conference on IC Design and Technology.

Optimizing the Readout Bias for the Capacitorless 1T Bulk FinFET RAM Cell

N. Collaert, J. Van Houdt, M. Jurczak, 2009, IEEE Electron Device Letters.

Realizing super-steep subthreshold slope with conventional FDSOI CMOS at low-bias voltages

J. G. Fossum, N. Collaert, M. Jurczak, 2010, 2010 International Electron Devices Meeting.

TCAD modeling and characterization of short-range variations in multiple-gate devices and circuit blocks

E. Baravelli, N. Speciale, M. Jurczak, 2008, 2008 15th International Conference on Mixed Design of Integrated Circuits and Systems.

The device architecture dilemma for CMOS technologies: Opportunities & challenges of finFET over planar MOSFET

B. Parvais, R. Rooyackers, A. Mercha, 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

Impact of Stochastic Mismatch on Measured SRAM Performance of FinFETs with Resist/Spacer-Defined Fins: Role of Line-Edge-Roughness

R. Rooyackers, A. Mercha, E. Augendre, 2006, 2006 International Electron Devices Meeting.

Multi-gate devices for the 32nm technology node and beyond

R. Rooyackers, A. Mercha, L. Witters, 2007, ESSDERC 2007 - 37th European Solid State Device Research Conference.

Review of FINFET technology

N. Collaert, A. Veloso, S. Biesemans, 2009, 2009 IEEE International SOI Conference.

Exploration of the Circuit Potential of Multiple-Gate Field-Effect Transistors

S. Severi, E. Augendre, N. Collaert, 2006, 2006 IEEE international SOI Conferencee Proceedings.

Evidences of anodic-oxidation reset mechanism in TiN\NiO\Ni RRAM cells

R. Degraeve, L. Goux, B. Govoreanu, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Analysis of the parasitic S/D resistance in multiple-gate FETs

N. Collaert, M. Jurczak, A. Dixit, 2005, IEEE Transactions on Electron Devices.

Reliability issues in MuGFET nanodevices

B. Kaczer, N. Collaert, D. Linten, 2008, 2008 IEEE International Reliability Physics Symposium.

Experimental investigation of the impact of line-edge roughness on MOSFET performance and yield

R. Rooyackers, W. Sansen, S. Decoutere, 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..

Enhanced Performance of PMOS MUGFET via Integration of Conformal Plasma-Doped Source/Drain Extensions

R. Rooyackers, T. Skotnicki, N. Collaert, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Carrier Mobility in Undoped Triple-Gate FinFET Structures and Limitations of Its Description in Terms of Top and Sidewall Channel Mobilities

V. Kilchytska, D. Flandre, N. Collaert, 2008, IEEE Transactions on Electron Devices.

Analog and RF circuits in 45 nm CMOS and below: planar bulk versus FinFET

B. Parvais, A. Mercha, S. Decoutere, 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node

R. Rooyackers, N. Collaert, R. Jonckheere, 2004, IEEE Electron Device Letters.

Experimental verification of SRAM cell functionality after hard and soft gate oxide breakdowns

E. Augendre, R. Degraeve, B. Kaczer, 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..

Demonstration of recessed SiGe S/D and inserted metal gate on HfO/sub 2/ for high performance pFETs.

R. Rooyackers, G. Eneman, S. Biesemans, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Scalability of the Si/sub 1-x/Ge/sub x/ source/drain technology for the 45-nm technology node and beyond

R. Rooyackers, Kristin De Meyer, F. Nouri, 2006, IEEE Transactions on Electron Devices.

Reliability of low current filamentary HfO2 RRAM discussed in the framework of the hourglass SET/RESET model

R. Degraeve, L. Goux, B. Govoreanu, 2012, 2012 IEEE International Integrated Reliability Workshop Final Report.

A novel CBRAM integration using subtractive dry-etching process of Cu enabling high-performance memory scaling down to 10nm node

L. Goux, N. Jossart, M. Jurczak, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Scalability of valence change memory: From devices to tip-induced filaments

Wilfried Vandervorst, Robin Degraeve, L. Goux, 2016 .

Full-field EUV and immersion lithography integration in 0.186μm2 FinFET 6T-SRAM cell

B. Parvais, R. Rooyackers, K. Ronse, 2008, 2008 IEEE International Electron Devices Meeting.

Influence of Fin Width on the Total Dose Behavior of p-Channel Bulk MuGFETs

P. Leroux, E. Simoen, C. Claeys, 2010, IEEE Electron Device Letters.

A systematic study of trade-offs in engineering a locally strained pMOSFET

R. Rooyackers, I. De Wolf, F. Nouri, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si/sub 0.8/Ge/sub 0.2/ in the source and drain regions

R. Rooyackers, N. Collaert, G. Eneman, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Metal Gate Technology using a Dy2O3 Dielectric Cap Approach for multiple-VT in NMOS FinFETs

S. Van Elshocht, B. Kaczer, P. Lehnen, 2007, 2007 IEEE International SOI Conference.

Hourglass concept for RRAM: A dynamic and statistical device model

R. Degraeve, L. Goux, B. Govoreanu, 2014, Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).

Advanced a-VMCO resistive switching memory through inner interface engineering with wide (>102) on/off window, tunable μA-range switching current and excellent variability

B. Govoreanu, H. Bender, M. Jurczak, 2016, 2016 IEEE Symposium on VLSI Technology.

SON (silicon on nothing)-a new device architecture for the ULSI era

T. Skotnicki, R. Pantel, M. Jurczak, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

Study on Enhanced Performance in NMOSFETs on Strained Silicon

T. Skotnicki, D. Bensahel, Y. Campidelli, 1999, 29th European Solid-State Device Research Conference.

GIDL (gate-induced drain leakage) and parasitic schottky barrier leakage elimination in aggressively scaled HfO/sub 2/TiN FinFET devices

R. Rooyackers, N. Collaert, S. Biesemans, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Postcycling LRS Retention Analysis in HfO2/Hf RRAM 1T1R Device

R. Degraeve, L. Goux, B. Govoreanu, 2013, IEEE Electron Device Letters.

Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency

R. Rooyackers, E. Augendre, N. Collaert, 2006, 2006 International Electron Devices Meeting.

RPN Oxynitride Gate Dielectrics for 90 nm Low Power CMOS Applications

R. Rooyackers, A. Veloso, M. Jurczak, 2002, 32nd European Solid-State Device Research Conference.

On the Variability of the Front-/Back-Channel LF Noise in UTBOX SOI nMOSFETs

E. Simoen, C. Claeys, T. Nicoletti, 2013, IEEE Transactions on Electron Devices.

Metal gate thickness optimization for MuGFET performance improvement

S. Van Elshocht, N. Collaert, J. Swerts, 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.

Performance and reliability of Ultra-Thin HfO2-based RRAM (UTO-RRAM)

R. Degraeve, L. Goux, B. Govoreanu, 2013, 2013 5th IEEE International Memory Workshop.

Validation of Retention Modeling as a Trap-Profiling Technique for SiN-Based Charge-Trapping Memories

R. Degraeve, L. Breuil, J. Van Houdt, 2010, IEEE Electron Device Letters.

Process-improved RRAM cell performance and reliability and paving the way for manufacturability and scalability for high density memory application

B. Govoreanu, A. Fantini, N. Jossart, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate lengths

T. Chiarella, C. Vrancken, A. Veloso, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Understanding the optimization of sub-45nm FinFET devices for ESD applications

C. Duvvury, N. Collaert, D. Linten, 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach

R. Rooyackers, B. Kaczer, S. Locorotondo, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Schottky-Barrier Height Lowering by an Increase of the Substrate Doping in PtSi Schottky Barrier Source/Drain FETs

E. Augendre, S. Biesemans, M. Jurczak, 2007, IEEE Electron Device Letters.

Programming-conditions solutions towards suppression of retention tails of scaled oxide-based RRAM

R. Degraeve, L. Goux, A. Fantini, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Minimization of the MuGFET contact resistance by integration of NiSi contacts on epitaxially raised source/drain regions

R. Rooyackers, N. Collaert, S. Biesemans, 2005, Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005..

Reliability Comparison of Triple-Gate Versus Planar SOI FETs

R. Degraeve, B. Kaczer, E. Simoen, 2006, IEEE Transactions on Electron Devices.

RTN insight to filamentary instability and disturb immunity in ultra-low power switching HfOx and AlOx RRAM

R. Degraeve, L. Goux, A. Fantini, 2013, 2013 Symposium on VLSI Technology.

Reliability of Strained-Si Devices With Post-Oxide-Deposition Strain Introduction

E. San Andres, R. Degraeve, B. Kaczer, 2008, IEEE Transactions on Electron Devices.

Conductive-AFM tomography for 3D filament observation in resistive switching devices

L. Goux, H. Bender, W. Vandervorst, 2013, 2013 IEEE International Electron Devices Meeting.

Dual Work Function Phase Controlled Ni-FUSI CMOS (NiSi NMOS, Ni2Si or Ni31Si12 PMOS): Manufacturability, Reliability & Process Window Improvement by Sacrificial SiGe Cap

S. Locorotondo, H. Bender, T. Chiarella, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

RTN-based defect tracking technique: Experimentally probing the spatial and energy profile of the critical filament region and its correlation with HfO2RRAM switching operation and failure mechanism

E. Simoen, Z. Chai, B. Govoreanu, 2016, 2016 IEEE Symposium on VLSI Technology.

Demonstration of Asymmetric Gate Oxide Thickness 4-Terminal FinFETs

M. Masahara, L. Witters, C. Vrancken, 2006, 2006 IEEE international SOI Conferencee Proceedings.

Scalability of strained nitride capping layers for future CMOS generations

G. Eneman, M. Jurczak, K. De Meyer, 2005, Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005..

Elevated Co-Silicide for sub-100nm High Performance and RF CMOS

R. Rooyackers, E. Augendre, W. Jeamsaksiri, 2002, 32nd European Solid-State Device Research Conference.

Investigation on the Suitability of Vertical MOSFET's for High Speed (RF) CMOS Applications

T. Skotnicki, M. Jurczak, R. Gwoziecki, 1998, 28th European Solid-State Device Research Conference.

90nm W\Al2O3\TiW\Cu 1T1R CBRAM cell showing low-power, fast and disturb-free operation

L. Goux, A. Fantini, M. Jurczak, 2013, 2013 5th IEEE International Memory Workshop.

Statistical investigation of the floating gate memory cell leakage through high-k interpoly dielectrics and its impact on scalability and reliability

R. Degraeve, B. Govoreanu, J. Van Houdt, 2008, 2008 IEEE International Electron Devices Meeting.

Optimization of the MuGFET performance on Super Critical-Strained SOI (SC-SSOI) substrates featuring raised source/drain and dual CESL

B. Ghyselen, R. Rooyackers, E. Augendre, 2007, 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).

Performance and Reliability of Strained-Silicon nMOSFETs With SiN Cap Layer

E. Simoen, G. Giusi, G. Eneman, 2007, IEEE Transactions on Electron Devices.

Demonstration of Asymmetric Gate-Oxide Thickness Four-Terminal FinFETs Having Flexible Threshold Voltage and Good Subthreshold Slope

M. Masahara, L. Witters, C. Vrancken, 2007, IEEE Electron Device Letters.

A Self-Aligned, Electrically Separable Double-Gate MOS Transistor Technology for Dynamic Threshold Voltage Application

Michel Haond, Stephane Monfray, Thomas Skotnicki, 2003 .

Negligible Effect of Process-Induced Strain on Intrinsic NBTI Behavior

B. Kaczer, G. Eneman, G. Groeseneken, 2007, IEEE Electron Device Letters.

Low Vt Ni-FUSI CMOS Technology using a DyO cap layer with either single or dual Ni-phases

S. Van Elshocht, P. Lehnen, C. Vrancken, 2007, 2007 IEEE Symposium on VLSI Technology.

Integration challenges for multi-gate devices

R. Rooyackers, S. De Gendt, S. Locorotondo, 2005, 2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005..

In-depth characterization of the hole mobility in 50-nm process-induced strained MOSFETs

G. Ghibaudo, F. Andrieu, T. Ernst, 2005, IEEE Electron Device Letters.

On the origin of the mobility reduction in bulk-Si, UTBOX-FDSOI and SiGe devices with ultrathin-EOT dielectrics

N. Collaert, J. Mitard, M. Jurczak, 2011, Proceedings of 2011 International Symposium on VLSI Technology, Systems and Applications.

Trap Spectroscopy by Charge Injection and Sensing (TSCIS): A quantitative electrical technique for studying defects in dielectric stacks

R. Degraeve, B. Kaczer, B. Govoreanu, 2008, 2008 IEEE International Electron Devices Meeting.

Retention, disturb and variability improvements enabled by local chemical-potential tuning and controlled Hour-Glass filament shape in a novel W\WO3\Al2O3\Cu CBRAM

R. Degraeve, L. Goux, A. Fantini, 2016, 2016 IEEE Symposium on VLSI Technology.

Experimental Investigation of Optimum Gate Workfunction for CMOS Four-Terminal Multigate MOSFETs (MUGFETs)

M. Masahara, L. Witters, C. Vrancken, 2007, IEEE Transactions on Electron Devices.

On the Bipolar and Unipolar Switching Mechanisms Observed in NiO Memory Cells Made by Thermal Oxidation of Ni

L. Goux, M. Jurczak, J. G. Lisoni, 2009, 2009 IEEE International Memory Workshop.

Dopant and carrier profiling in FinFET-based devices with sub-nanometer resolution

P. Eyben, L. Witters, N. Collaert, 2010, 2010 Symposium on VLSI Technology.

Frequency Variation of the Small-Signal Output Conductance of Decananometer MOSFETs Due to Substrate Crosstalk

V. Kilchytska, D. Flandre, N. Collaert, 2007, IEEE Electron Device Letters.

Understanding of the intrinsic characteristics and memory trade-offs of sub-μA filamentary RRAM operation

R. Degraeve, L. Goux, A. Fantini, 2013, 2013 Symposium on VLSI Technology.

Scalability of Stress Induced by Contact-Etch-Stop Layers: A Simulation Study

G. Eneman, M. Jurczak, K. De Meyer, 2007, IEEE Transactions on Electron Devices.

High performance 40 nm vertical MOSFET within a conventional CMOS process flow

T. Skotnicki, A. Villaret, M. Jurczak, 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

Impact of Back-Gate Bias and Device Geometry on the Total Ionizing Dose Response of 1-Transistor Floating Body RAMs

B. L. Bhuva, N. N. Mahatme, E. Simoen, 2012, IEEE Transactions on Nuclear Science.

Dielectric pockets-a new concept of the junctions for deca-nanometric CMOS devices

Stephane Monfray, Thomas Skotnicki, M. Jurczak, 2001 .

Hydrogen-Induced Resistive Switching in TiN/ALD $ \hbox{HfO}_{2}$/PEALD TiN RRAM Device

L. Goux, J. Swerts, G. Groeseneken, 2012, IEEE Electron Device Letters.

Optimization of Sub-Melt Laser Anneal: Performance and Reliability

S. Mahapatra, S. Severi, L. Pantisano, 2006, 2006 International Electron Devices Meeting.

Dielectric pockets – a new concept of the junctions for deca-nanometric CMOS devices

T. Skotnicki, S. Monfray, D. Dutartre, 2000, 30th European Solid-State Device Research Conference.

Experimental Evidence for Reduction of Gate Tunneling Current in FinFET Structures and Its Dependence on the Fin Width

V. Kilchytska, D. Flandre, N. Collaert, 2006, 2006 European Solid-State Device Research Conference.

Specific features of the capacitance and mobility behaviors in FinFET structures

V. Kilchytska, D. Flandre, R. Rooyackers, 2005, Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005..

Characterization and Optimization of Sub-32-nm FinFET Devices for ESD Applications

R. Rooyackers, C. Duvvury, N. Collaert, 2008, IEEE Transactions on Electron Devices.

Ultra-thin oxynitride gate dielectrics by pulsed-RF DPN for 65 nm general purpose CMOS applications

R. Degraeve, A. Veloso, M. Jurczak, 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..

CMOS integration of dual work function phase controlled Ni FUSI with simultaneous silicidation of NMOS (NiSi) and PMOS (Ni-rich silicide) gates on HfSiON

S. Locorotondo, T. Chiarella, C. Vrancken, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Tailoring switching and endurance / retention reliability characteristics of HfO2 / Hf RRAM with Ti, Al, Si dopants

R. Degraeve, L. Goux, B. Govoreanu, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.