A. J. van Genderen

发表

SPACE USER’S MANUAL

N. P. van der Meijs, A. J. van Genderen, Frederik Beeftink, 2001 .

Boundary element methods for 3D capacitance and substrate resistance calculations in inhomogeneous media in a VLSI layout verification package

N. P. van der Meijs, T. Smedes, A. J. van Genderen, 1994 .

Reduced RC models for IC interconnections with coupling capacitances

N. P. van der Meijs, A. J. van Genderen, 1992 .

SPACE 3D CAPACITANCE EXTRACTION USER'S MANUAL

N. P. van der Meijs, A. J. van Genderen, 1997 .

Space-efficient extraction algorithms

N. P. van der Meijs, A. J. van Genderen, 1992 .

Parasitics in VLSI Circuits and the Role of Layout Verification

N. P. van der Meijs, A. J. van Genderen, 2007 .

Extracting simple but accurate RC models for VLSI interconnect

N. P. van der Meijs, A. J. van Genderen, 1988 .

SLS : SWITCH-LEVEL SIMULATOR USER'S MANUAL

A. J. van Genderen, A. C. de Graaf, 1994 .

Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures

N. P. van der Meijs, A. J. van Genderen, 1993, ICCAD 1993.

A frontal computation scheme for the Schur algorithm to efficiently solve large boundary-element problems

N. P. van der Meijs, A. J. van Genderen, 1992 .

An efficient algorithm for analysis of non-orthogonal layout

N. P. van der Meijs, A. J. van Genderen, 1989 .

Reduced models for the behavior of VLSI circuits

A. J. van Genderen, 1991 .