Soon-Jyh Chang

发表

Histogram Based Testing Strategy for ADC

Bin-Da Liu, Hsin-Wen Ting, Soon-Jyh Chang, 2006, 2006 15th Asian Test Symposium.

Resistor-Based Temperature Sensing Chip with Digital Output

Soon-Jyh Chang, Kai-Min Chang, Yen-Ju Lin, 2020, 2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Analysis of Nonideal Behaviors Based on INL/DNL Plots for SAR ADCs

Hsin-Wen Ting, Soon-Jyh Chang, Chun-Po Huang, 2016, IEEE Transactions on Instrumentation and Measurement.

A Histogram-Based Testing Method for Estimating A/D Converter Performance

Hsin-Wen Ting, Soon-Jyh Chang, Bin-Da Liu, 2008, IEEE Transactions on Instrumentation and Measurement.

A 10-bit 60-MS/s Low-Power Pipelined ADC With Split-Capacitor CDS Technique

Soon-Jyh Chang, Chun-Cheng Liu, Jin-Fu Lin, 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 10-fJ/bit/dB half-rate equalizer with charge-average switched-capacitor summation technique

Soon-Jyh Chang, Yen-Long Lee, 2016, 2016 5th International Symposium on Next-Generation Electronics (ISNE).

A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS

Soon-Jyh Chang, Yen-Ting Liu, Ying-Zu Lin, 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 11-bit 35-MS/s wide input range SAR ADC in 180-nm CMOS process

Soon-Jyh Chang, Chun-Po Huang, Wen-Chia Luo, 2018, 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

A pipeline ADC with latched-based ring amplifiers

Soon-Jyh Chang, Chun-Po Huang, Ya-Ting Shyu, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits

Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen, 2003, J. Inf. Sci. Eng..

A Low-Cost Output Response Analyzer Circuit for ADC BIST

Hsin-Wen Ting, Soon-Jyh Chang, Bin-Da Liu, 2009, 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis.

An Unbounded Frequency Detection Mechanism for Continuous-Rate CDR Circuits

Yen-Chi Chen, Soon-Jyh Chang, Yen-Long Lee, 2017, IEEE Transactions on Circuits and Systems II: Express Briefs.

Detection System for Capacitive Plantar Pressure Monitoring

Soon-Jyh Chang, Tzung-Min Tsai, Shuenn-Yuh Lee, 2020, IEEE Access.

Heart rate detection through bone-conduction headset

Soon-Jyh Chang, Shuenn-Yuh Lee, Tzung-Min Tsai, 2014, 2014 IEEE Biomedical Circuits and Systems Conference (BioCAS) Proceedings.

A low power duobinary voltage mode transmitter

Soon-Jyh Chang, Yen-Long Lee, Ming-Hung Chien, 2017, 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

A Single Opamp Third-Order Low-Distortion Delta-Sigma Modulator with SAR Quantizer Embedded Passive Adder

Soon-Jyh Chang, Chun-Yueh Huang, Bin-Da Liu, 2014, IEICE Trans. Electron..

A SAR ADC BIST for simplified linearity test

Hsin-Wen Ting, Soon-Jyh Chang, An-Sheng Chao, 2011, 2011 IEEE International SOC Conference.

Low-Power Circuit Techniques for Low-Voltage Pipelined ADCs Based on Switched-Opamp Architecture

Soon-Jyh Chang, Bin-Da Liu, Hsin-Hung Ou, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A 5-bit 1.35-GSPS DAC for UWB transceivers

Soon-Jyh Chang, Ren-Li Chen, 2009, 2009 IEEE International Conference on Ultra-Wideband.

A 6-bit 1GS/s low-power flash ADC

Soon-Jyh Chang, Ying-Zu Lin, Yu-Chang Lien, 2009 .

A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang- Bang CDRs

Hsin-Wen Ting, Soon-Jyh Chang, Yen-Long Lee, 2018, IEEE Design & Test.

A Versatile Step-Up/Step-Down Switched-Capacitor-Based DC-DC Converter

Soon-Jyh Chang, Bin-Da Liu, Chien-Hung Tsai, 2008, IEICE Trans. Electron..

A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme

Soon-Jyh Chang, Ying-Zu Lin, Cheng-Wu Lin, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

2012 JETTA Reviewers

Luigi Carro, Fernando Morgado Dias, Irith Pomeranz, 2013, J. Electron. Test..

A 1-V, 44.6 ppm/°C bandgap reference with CDS technique

Soon-Jyh Chang, Chung-Ming Huang, Peng-Yu Chen, 2012, Proceedings of Technical Program of 2012 VLSI Design, Automation and Test.

An on-chip concurrent high frequency analog and digital sinusoidal generator

Bin-Da Liu, Hsin-Wen Ting, Soon-Jyh Chang, 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

The SoC design of a versatile biomedical signal processor for potentiostat

Chung-Ho Chen, Bin-Da Liu, Soon-Jyh Chang, 2015, 2015 International Symposium on Bioelectronics and Bioinformatics (ISBB).

An Efficient Design-for-Testability Scheme for Motion Estimation in H.264/AVC

Yi-Lin Tsai, Soon-Jyh Chang, Tung-Hsing Wu, 2007, 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

A 12-bit 40-MS/s calibration-free SAR ADC

Soon-Jyh Chang, Chun-Po Huang, Li-Jen Chang, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs

Jai-Ming Lin, Soon-Jyh Chang, Chun-Po Huang, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Digitally Calibrated Current-Voltage Feedback Transconductor in 0.13-μm CMOS Process

Soon-Jyh Chang, Ying-Zu Lin, Yen-Ting Liu, 2006, 2006 IEEE Asian Solid-State Circuits Conference.

A 12-b 40-MS/s Calibration-Free SAR ADC

Soon-Jyh Chang, Chun-Po Huang, Li-Jen Chang, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST

Hsin-Wen Ting, Soon-Jyh Chang, Bin-Da Liu, 2007, J. Electron. Test..

Routing-aware placement algorithms for modern analog integrated circuits

Jai-Ming Lin, Soon-Jyh Chang, Chun-Po Huang, 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

A 925 MHz 1.4μW wireless energy-harvesting circuit with error-correction ASK demodulation for RFID healthcare system

Soon-Jyh Chang, Shuenn-Yuh Lee, Tzung-Min Tsai, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

A 5-bit 4.2-GS/s Flash ADC in 0.13-µm CMOS Process

Soon-Jyh Chang, Ying-Zu Lin, Yen-Ting Liu, 2009, IEICE Trans. Electron..

A 10-bit 50-MS/s SAR ADC for dual-voltage domain portable systems

Chun-Jen Chen, Soon-Jyh Chang, Che-Hsun Kuo, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

A 3.9-fJ/c.-s. 0.5-V 10-bit 100-kS/s low power SAR ADC with time-based fixed window

Soon-Jyh Chang, Cheng-Hsun Ho, Guan-Ying Huang, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

An area- and power-efficient half-rate clock and data recovery circuit

Yen-Chi Chen, Chung-Ming Huang, Soon-Jyh Chang, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

A Systematic Design Methodology of Asynchronous SAR ADCs

Jai-Ming Lin, Soon-Jyh Chang, Chun-Po Huang, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-µm digital CMOS process

Yi-Ting Huang, Chung-Ming Huang, Soon-Jyh Chang, 2009, 2009 International Symposium on VLSI Design, Automation and Test.

Low power pipelined SAR ADC with loading-free architecture

Soon-Jyh Chang, Chun-Po Huang, Guan-Ying Huang, 2014, Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test.

A bias-driven approach for automated design of operational amplifiers

Soon-Jyh Chang, Ya-Ting Shyu, Cheng-Wu Lin, 2009, 2009 International Symposium on VLSI Design, Automation and Test.

A dual-edge sampling CES delay-locked loop based clock and data recovery circuits

Soon-Jyh Chang, Yen-Long Lee, Jih Ren Goh, 2015, VLSI Design, Automation and Test(VLSI-DAT).

Routability-driven placement algorithm for analog integrated circuits

Jai-Ming Lin, Soon-Jyh Chang, Cheng-Wu Lin, 2012, ISPD '12.

A power-efficient 0.8 V, 9-bit, 20-MS/s pipelined ADC with opamp-shared loading-free architecture

Bin-Da Liu, Soon-Jyh Chang, Hsin-Hung Ou, 2008, 2008 International Conference on Communications, Circuits and Systems.

A DFT for semi-DC fault diagnosis for switched-capacitor circuits

Soon-Jyh Chang, Chung Len Lee, Sheng-Jer Kuo, 1999, European Test Workshop 1999 (Cat. No.PR00390).

A systematic design automation approach for flash ADCs

Soon-Jyh Chang, Chun-Po Huang, Ya-Ting Shyu, 2010, 2010 International Symposium on Next Generation Electronics.

A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS

Soon-Jyh Chang, Yen-Ting Liu, Ying-Zu Lin, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A Third-Order Low-Distortion Delta-Sigma Modulator with Opamp Sharing and Relaxed Feedback Path Timing

Hsin-Wen Ting, Soon-Jyh Chang, Chun-Yueh Huang, 2012, IEICE Trans. Electron..

Low-Power and Wide-Bandwidth Cyclic ADC With Capacitor and Opamp Reuse Techniques for CMOS Image Sensor Application

Soon-Jyh Chang, Hann-Huei Tsai, Jin-Fu Lin, 2009, IEEE Sensors Journal.

A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique

Soon-Jyh Chang, Jin-Fu Lin, 2006, 2006 IEEE International Symposium on Circuits and Systems.

A Jitter Characterizing BIST with Pulse-Amplifying Technique

Soon-Jyh Chang, An-Sheng Chao, Soon-Jyh Chang, 2009, 2009 Asian Test Symposium.

A 10b 200MS/s 0.82mW SAR ADC in 40nm CMOS

Soon-Jyh Chang, Chun-Po Huang, Ying-Zu Lin, 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A quick jitter tolerance estimation technique for bang-bang CDRs

Soon-Jyh Chang, Yen-Long Lee, 2017, 2017 International Test Conference in Asia (ITC-Asia).

A 0.35-1 V 0.2-3 GS/s 4-bit low-power flash ADC for a solar-powered wireless module

Soon-Jyh Chang, Ying-Zu Lin, Yu-Chang Lien, 2010, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test.

A 6-bit 1GS/s low-power flash ADC

Soon-Jyh Chang, Ying-Zu Lin, Yu-Chang Lien, 2009, 2009 International Symposium on VLSI Design, Automation and Test.

A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation

Chung-Ming Huang, Soon-Jyh Chang, Ying-Zu Lin, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Analyses of Splittable Amplifier Technique and Cancellation of Memory Effect for Opamp Sharing

Bin-Da Liu, Hsin-Wen Ting, Soon-Jyh Chang, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design of high-resolution pipelined analog-to-digital converters using multiple-phase capacitor-splitting feedback interchange technique

Kuen-Jong Lee, Soon-Jyh Chang, Chih-Haur Huang, 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

A 3rd-order delta-sigma modulator with timing-sharing opamp-sharing technique

Soon-Jyh Chang, Chun-Yueh Huang, Bin-Da Liu, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

A current compensated reference oscillator

Soon-Jyh Chang, Ying-Zu Lin, Wan-Jing Li, 2009, 2009 International Symposium on VLSI Design, Automation and Test.

A first-order low distortion sigma-delta modulator using split DWA technique and SAR quantizer

Soon-Jyh Chang, Chun-Po Huang, I-Jen Chao, 2015, VLSI Design, Automation and Test(VLSI-DAT).

A sigma-delta modulation based BIST scheme for A/D converters

Kuen-Jong Lee, Soon-Jyh Chang, Ruei-Shiuan Tzeng, 2003, 2003 Test Symposium.

A 0.5-TO-4 GBPS continuous-rate clock and data recovery circuit with bidirectional frequency detection

Soon-Jyh Chang, Yen-Chi Chen, Yen Long Lee, 2014 .

An 8-bit 400-MS/s calibration-free SAR ADC with a pre-amplifier-only comparator

Soon-Jyh Chang, Hao-Sheng Wu, Chih-Huei Hou, 2017, 2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

10-bit 30-MS/s SAR ADC Using a Switchback Switching Method

Soon-Jyh Chang, Ying-Zu Lin, Guan-Ying Huang, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 10b 100kS/s SAR ADC with charge recycling switching method

Soon-Jyh Chang, Ying-Zu Lin, Guan-Ying Huang, 2014, 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A Low-Power Mixed-Architecture ADC with Time-Interleaved Correlated Double Sampling Technique and Power-Efficient Back-End Stages

Soon-Jyh Chang, Jin-Fu Lin, 2011, IEICE Trans. Electron..

A 10-bit 50-MS/s SAR ADC with techniques for relaxing the requirement on driving capability of reference voltage buffers

Soon-Jyh Chang, Chun-Po Huang, Guan-Ying Huang, 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Efficient Four-Coil Wireless Power Transfer for Deep Brain Stimulation

Soon-Jyh Chang, Lih-Yih Chiou, Chin-Lung Yang, 2017, IEEE Transactions on Microwave Theory and Techniques.

A Reduced Code Linearity Test Method for Pipelined A/D Converters

Soon-Jyh Chang, Jin-Fu Lin, Te-Chieh Kung, 2008, 2008 17th Asian Test Symposium.

A 2-GS/s 8b Flash-SAR Time-Interleaved ADC with Background Offset Calibration

Soon-Jyh Chang, Yi-Shen Cheng, Huan-Jui Hu, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

A 10-bit 1-GS/s 2x-Interleaved Timing-Skew Calibration Free SAR ADC

Soon-Jyh Chang, Yi-Shen Cheng, Huan-Jui Hu, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

Transition-Code Based Linearity Test Method for Pipelined ADCs With Digital Error Correction

Hsin-Wen Ting, Soon-Jyh Chang, Jin-Fu Lin, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 6-bit Current-Steering DAC With Compound Current Cells for Both Communication and Rail-to-Rail Voltage-Source Applications

Soon-Jyh Chang, Ren-Li Chen, 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

A successive approximation ADC with resistor-capacitor hybrid structure

Soon-Jyh Chang, Guan-Ying Huang, Ting-Zi Chen, 2013, 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT).

AnEfficient Design-for-Testability SchemeforMotion Estimation in H.264/AVC

Yi-Lin Tsai, Soon-Jyh Chang, Tung-Hsing Wu, 2007 .

A 5 Gb/s 1/4-rate clock and data recovery circuit using dynamic stepwise bang-bang phase detector

Chung-Ming Huang, Soon-Jyh Chang, Ying-Zu Lin, 2012, 2012 IEEE Asian Solid State Circuits Conference (A-SSCC).

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

Soon-Jyh Chang, Ying-Zu Lin, Guan-Ying Huang, 2010, IEEE Journal of Solid-State Circuits.

A power-efficient sizing methodology of SAR ADCs

Soon-Jyh Chang, Chun-Po Huang, Guan-Ying Huang, 2012, 2012 IEEE International Symposium on Circuits and Systems.

A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding

Soon-Jyh Chang, Ying-Zu Lin, Guan-Ying Huang, 2012, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A gm/ID-based synthesis tool for pipelined analog to digital converters

Soon-Jyh Chang, Jin-Fu Lin, Ya-Ting Shyu, 2009, 2009 International Symposium on VLSI Design, Automation and Test.

A 9-bit 50 MS/s CBSC pipelined ADC using time-shifted correlated double sampling

Bin-Da Liu, Soon-Jyh Chang, Chun-Yueh Huang, 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop

Soon-Jyh Chang, Lih-Yih Chiou, Yen-Ting Liu, 2006, 2006 IEEE International Symposium on Circuits and Systems.

A Low Energy Consumption 10-Bit 100kS/s SAR ADC with Timing Control Adaptive Window

Soon-Jyh Chang, Chun-Po Huang, Chih-Yuan Kung, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

A 2-GS/s 6-bit flash ADC with offset calibration

Soon-Jyh Chang, Ying-Zu Lin, Cheng-Wu Lin, 2008, 2008 IEEE Asian Solid-State Circuits Conference.

A 1V 11fJ/conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18µm CMOS

Chung-Ming Huang, Soon-Jyh Chang, Ying-Zu Lin, 2010, 2010 Symposium on VLSI Circuits.

A 1-V CDS bandgap reference without on-chip resistors

Chung-Ming Huang, Soon-Jyh Chang, Jin-Fu Lin, 2012, 2012 IEEE Asia Pacific Conference on Circuits and Systems.

Six-bit 2.7-GS/s 5.4-mW Nyquist complementary metal-oxide semiconductor digital-to-analogue converter for ultra-wideband transceivers

Hsin-Wen Ting, Soon-Jyh Chang, Ren-Li Chen, 2012, IET Circuits Devices Syst..

A Design of Linearity Built-in Self-Test for Current-Steering DAC

Hsin-Wen Ting, Soon-Jyh Chang, Su-Ling Huang, 2011, J. Electron. Test..

A time domain built-in self-test methodology for SNDR and ENOB tests of analog-to-digital converters

Hsin-Wen Ting, Soon-Jyh Chang, Bin-Da Liu, 2004, 13th Asian Test Symposium.

Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits

Jai-Ming Lin, Soon-Jyh Chang, Chung-Lin Lee, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors

Jai-Ming Lin, Soon-Jyh Chang, Chun-Po Huang, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Modified BER Test for SAR ADCs

Soon-Jyh Chang, Chia-Chuan Li, 2020, 2020 IEEE International Test Conference in Asia (ITC-Asia).

A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS

Soon-Jyh Chang, Ying-Zu Lin, Yen-Ting Liu, 2007, 2007 IEEE Custom Integrated Circuits Conference.

A 7 Gb/s half-rate clock and data recovery circuit with compact control loop

Soon-Jyh Chang, Yen-Long Lee, Yu-Po Cheng, 2016, 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Built-in high resolution signal generator for testing ADC and DAC

Soon-Jyh Chang, Chee-Kian Ong, Yeong-Jar Chang, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops

Jai-Ming Lin, Soon-Jyh Chang, Chun-Po Huang, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling

Chung-Ho Chen, Kuen-Jong Lee, Jai-Ming Lin, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS

Soon-Jyh Chang, Ying-Zu Lin, Guan-Ying Huang, 2011, IEEE Asian Solid-State Circuits Conference 2011.

Behavior model for comparator-based switched-capacitor SDM with relaxed DEM timing

Bin-Da Liu, Soon-Jyh Chang, Chun-Yueh Huang, 2010, The 2010 International Conference on Green Circuits and Systems.

A low-cost diagnosis methodology for pipelined A/D converters

Kuen-Jong Lee, Soon-Jyh Chang, Chih-Haur Huang, 2004, 13th Asian Test Symposium.

A capacitance-ratio quantification design for linearity test in differential top-plate sampling sar ADCS

Hsin-Wen Ting, Soon-Jyh Chang, An-Sheng Chao, 2015, Int. J. Circuit Theory Appl..

Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique

Soon-Jyh Chang, Jin-Fu Lin, Chih-Hao Huang, 2009, 2009 Asian Test Symposium.

A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process

Soon-Jyh Chang, Guan-Ying Huang, Chun-Cheng Liu, 2009, 2009 Symposium on VLSI Circuits.

An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video Coders

Hui-Hsien Tsai, Soon-Jyh Chang, Jar-Ferr Yang, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC in 90-nm CMOS process

Ying-Zong Juang, Soon-Jyh Chang, Chun-Po Huang, 2016, 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

A Digitally Calibrated CMOS Transconductor With a 100-MHz Bandwidth and 75-dB SFDR

Soon-Jyh Chang, Yen-Ting Liu, Ying-Zu Lin, 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

Conditional capacitor averaging technique to reduce nonlinearity induced by capacitor mismatch in 2.5-bit/stage pipelined ADCs

Soon-Jyh Chang, Jin-Fu Lin, Chih-Hao Huang, 2010, 2010 International Symposium on Next Generation Electronics.

Reconstructive Oscillator Based Sinusoidal Signal Generator for ADC BIST

Bin-Da Liu, Hsin-Wen Ting, Soon-Jyh Chang, 2005, 2005 IEEE Asian Solid-State Circuits Conference.

A 5-bit 1 Gsample/s two-stage ADC with a new flash folded architecture

Soon-Jyh Chang, Ying-Zu Lin, Hung-Yu Huang, 2007, TENCON 2007 - 2007 IEEE Region 10 Conference.

AnEfficient Design-for-testa bility Schemefor2-D Transform inH.264Advanced VideoCoders

Hui-Hsien Tsai, Soon-Jyh Chang, Jar-Ferr Yang, 2006 .

A pipelined SAR ADC with loading-separating technique in 90-nm CMOS technology

Soon-Jyh Chang, Guan-Ying Huang, Sheng-Hsiung Lin, 2012, 2012 IEEE Asia Pacific Conference on Circuits and Systems.

A 6-Bit 2-GS/s Flash Aanlog-to-Digital Converter in 0.18-μm CMOS Process

Soon-Jyh Chang, Ying-Zu Lin, Yen-Ting Liu, 2006, 2006 IEEE Asian Solid-State Circuits Conference.

Structural Fault Based Specification Reduction for Testing Analog Circuits

Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen, 2002, J. Electron. Test..

A Noise-shaping SAR Assisted MASH 2-1 Sigma-Delta Modulator

Soon-Jyh Chang, Chia-Ling Wei, Yu-Sian Lin, 2020, 2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count

Soon-Jyh Chang, Yen-Ting Liu, Ying-Zu Lin, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications

Soon-Jyh Chang, Ying-Zu Lin, Guan-Ying Huang, 2012, IEEE Journal of Solid-State Circuits.

A Low-Cost Stimulus Design for Linearity Test in SAR ADCs

Hsin-Wen Ting, Soon-Jyh Chang, An-Sheng Chao, 2014, IEICE Trans. Electron..

Performance-driven analog placement considering boundary constraint

Jai-Ming Lin, Soon-Jyh Chang, Chun-Po Huang, 2010, Design Automation Conference.

A Primary-Auxiliary Temperature Sensing Scheme for Multiple Hotspots in System-on-a-Chips

Soon-Jyh Chang, Peng-Yu Chen, Guan-Ying Huang, 2014, IEEE Sensors Journal.

Oscillation-test technique for Buck voltage regulator

Le-Ren Chang-Chien, Soon-Jyh Chang, Jing-Yi Huang, 2010, 2010 Twenty-Fifth Annual IEEE Applied Power Electronics Conference and Exposition (APEC).

A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture

Soon-Jyh Chang, Bin-Da Liu, Hsin-Hung Ou, 2008, IEICE Trans. Electron..

Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits

Jai-Ming Lin, Soon-Jyh Chang, Chun-Po Huang, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

Functional test pattern generation for CMOS operational amplifier

Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen, 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

A 1.6-GS/s 8b Flash-SAR Time-Interleaved ADC with Top-Plate Residue Based Gain Calibration

Soon-Jyh Chang, Che-Wei Hsu, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

On-chip reference oscillators with process, supply voltage and temperature compensation

Soon-Jyh Chang, Peng-Yu Chen, Ying-Zu Lin, 2010, 2010 International Symposium on Next Generation Electronics.

A 10-bit 12-MS/s successive approximation ADC with 1.2-pF input capacitance

Soon-Jyh Chang, Ying-Zu Lin, Guan-Ying Huang, 2009, 2009 IEEE Asian Solid-State Circuits Conference.