Ming-Dou Ker

发表

ESD protection structure with inductor-triggered SCR for RF applications in 65-nm CMOS process

Ming-Hsien Tsai, Chun-Yu Lin, Li-Wei Chu, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

On-chip ESD protection design by using polysilicon diodes in CMOS technology for smart card application

Ming-Dou Ker, Tai-Ho Wang, 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

ESD protection design on T/R switch with embedded SCR in CMOS process

Ming-Dou Ker, Tao-Yi Hung, 2017, 2017 IEEE 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).

Modified LC-tank ESD protection design for 60-GHz RF applications

Ming-Hsien Tsai, Chun-Yu Lin, Li-Wei Chu, 2011, 2011 20th European Conference on Circuit Theory and Design (ECCTD).

How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on

Ming-Dou Ker, Hun-Hsien Chang, 1999 .

A new Schmitt trigger circuit in a 0.13-μm 1/2.5-V CMOS process to receive 3.3-V input signals

Ming-Dou Ker, Shih-Lun Chen, 2004, IEEE Trans. Circuits Syst. II Express Briefs.

Circuit Performance Degradation of Sample-and-Hold Amplifier Due to Gate-Oxide Overstress in a 130-nm CMOS Process

Ming-Dou Ker, Jung-Sheng Chen, 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

Design of Mixed-Voltage I/O Buffer by Using NMOS-Blocking Technique

Ming-Dou Ker, Shih-Lun Chen, 2006, IEEE Journal of Solid-State Circuits.

New transient detection circuit for electrical fast transient (EFT) protection design in display panels

Tung-Yang Chen, Ming-Dou Ker, Wan-Yen Lin, 2010, 2010 IEEE International Conference on Integrated Circuit Design and Technology.

Design of cost-efficient ESD clamp circuits for the power rails of CMOS ASIC's with substrate-triggering technique

Tung-Yang Chen, Ming-Dou Ker, Chung-Yu Wu, 1997, Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334).

The Impact of Gate-Oxide Breakdown on Common-Source Amplifiers With Diode-Connected Active Load in Low-Voltage CMOS Processes

Ming-Dou Ker, Jung-Sheng Chen, 2007, IEEE Transactions on Electron Devices.

Design of ESD protection cell for dual-band RF applications in a 65-nm CMOS process

Ming-Hsien Tsai, Chun-Yu Lin, Li-Wei Chu, 2012, Electrical Overstress / Electrostatic Discharge Symposium Proceedings 2012.

Overview on ESD Protection Designs of Low-Parasitic Capacitance for RF ICs in CMOS Technologies

Chun-Yu Lin, Ming-Dou Ker, Yuan-Wen Hsiao, 2011, IEEE Transactions on Device and Materials Reliability.

A 70nW, 0.3V temperature compensation voltage reference consisting of subthreshold MOSFETs in 65nm CMOS technology

Ming-Dou Ker, Ting-Chou Lu, Hsiao-Wen Zan, 2016, 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

A New Architecture for Charge Pump Circuit Without Suffering Gate-Oxide Reliability in Low-Voltage CMOS Processes

Ming-Dou Ker, Tzu-Ming Wang, Wan-Yi Shen, 2007, 2007 14th IEEE International Conference on Electronics, Circuits and Systems.

Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology

Ming-Dou Ker, Wen-Yu Lo, M. Ker, 2003 .

Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection

Ming-Dou Ker, Chih-Ting Yeh, 2010, IEEE Journal of Solid-State Circuits.

Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process

Ming-Dou Ker, Chia-Tsen Dai, Po-Yen Chiu, 2012, 2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Area-efficient layout design for output transistors with consideration of ESD reliability

Chung-Yu Wu, Ming-Dou Ker, Hun-Hsien Chang, 1996, Proceedings 1996 IEEE Hong Kong Electron Devices Meeting.

On-Chip HBM and HMM ESD Protection Design for RF Applications in 40-nm CMOS Process

Ming-Dou Ker, Chun-Yu Lin, Jie-Ting Chen, 2018, IEEE Transactions on Electron Devices.

Investigation on Latch-Up Path Between I/O PMOS and Core PMOS in a 0.18-μm CMOS Process

Ming-Dou Ker, Chun-Cheng Chen, 2019, 2019 IEEE International Reliability Physics Symposium (IRPS).

On the Design of Power-Rail ESD Clamp Circuits With Gate Leakage Consideration in Nanoscale CMOS Technology

Ming-Dou Ker, Chih-Ting Yeh, 2014, IEEE Transactions on Device and Materials Reliability.

Characterization of SOA in Time Domain and the Improvement Techniques for Using in High-Voltage Integrated Circuits

Ming-Dou Ker, Wen-Yi Chen, 2012, IEEE Transactions on Device and Materials Reliability.

A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control

Sheng-Fu Liang, Chung-Yu Wu, Ming-Dou Ker, 2018, IEEE Journal of Solid-State Circuits.

Evaluation on board-level noise filter networks to suppress transient-induced latchup under system-level ESD test

Ming-Dou Ker, Sheng-Fu Hsu, 2005, 2005 Electrical Overstress/Electrostatic Discharge Symposium.

An ESD-protected 5-GHz differential low-noise amplifier in a 130-nm CMOS process

Ming-Dou Ker, Yuan-Wen Hsiao, M. Ker, 2008, 2008 IEEE Custom Integrated Circuits Conference.

On the design of power-rail esd clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process

Ming-Dou Ker, Yeong-Jar Chang, Po-Yen Chiu, 2009, 2009 IEEE International Symposium on Circuits and Systems.

Area-efficient layout design for CMOS output transistors

Chung-Yu Wu, Ming-Dou Ker, Tain-Shun Wu, 1997 .

Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology

Ming-Dou Ker, Federico A. Altolaguirre, 2013, 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT).

Low-trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering

Ming-Dou Ker, Chun Chiang, Ping-Chen Chang, 2017, 2017 IEEE 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).

SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes

Ming-Dou Ker, Kuo-Chun Hsu, M. Ker, 2003 .

ESD-aware circuit design in CMOS integrated circuits to meet system-level ESD specification in microelectronic systems

Ming-Dou Ker, 2011, 2011 IEEE International Conference of Electron Devices and Solid-State Circuits.

Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations

Ming-Dou Ker, Kun-Hsien Lin, 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits

Ming-Dou Ker, Hui-Wen Tsai, Yi-Sheng Liu, 2013, 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT).

ESD implantations in 0.18-/spl mu/m salicided CMOS technology for on-chip ESD protection with layout consideration

Ming-Dou Ker, Che-Hao Chuang, 2001, Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548).

Optimization of broadband RF performance and ESD robustness by π-model distributed ESD protection scheme

Ming-Dou Ker, Yuan-Wen Hsiao, Bing-Jye Kuo, 2006 .

A bending N-Well ballast layout to improve ESD robustness in fully-silicided CMOS technology

Ming-Dou Ker, Wen-Yi Chen, Yong-Ru Wen, 2010, 2010 IEEE International Reliability Physics Symposium.

ESD buses for whole-chip ESD protection

Tung-Yang Chen, Ming-Dou Ker, Hun-Hsien Chang, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

應用於2.4GHz T/R開關前端電路之靜電放電防護設計

Ming-Dou Ker, 劉睿閎, Rui-Hong Liu, 2015 .

High-voltage-tolerant stimulator with adaptive loading consideration for electronic epilepsy prosthetic SoC in a 0.18-µm CMOS process

Chun-Yu Lin, Ming-Dou Ker, Yi-Ju Li, 2012, 10th IEEE International NEWCAS Conference.

Transient-to-Digital Converter for System-Level Electrostatic Discharge Protection in CMOS ICs

Ming-Dou Ker, Cheng-Cheng Yen, 2009, IEEE Transactions on Electromagnetic Compatibility.

Latchup-free ESD protection design with complementary substrate-triggered SCR devices

Ming-Dou Ker, Kuo-Chun Hsu, 2003 .

A new output buffer for 3.3-V PCI-X application in a 0.13-/spl mu/m 1/2.5-V CMOS process

Ming-Dou Ker, Shih-Lun Chen, 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.

Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-µm CMOS technology

Shih-Hung Chen, Ming-Dou Ker, 2010, Microelectron. Reliab..

Improve latch-up immunity by circuit solution

Ming-Dou Ker, Hui-Wen Tsai, 2015, 2015 IEEE 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Design and Analysis of On-Chip ESD Protection Circuit with Very Low Input Capacitance for High-Precision Analog Applications

Tung-Yang Chen, Chung-Yu Wu, Ming-Dou Ker, 2002 .

ESD protection design in a 0.18-/spl mu/m salicide CMOS technology by using substrate-triggered technique

Tung-Yang Chen, Ming-Dou Ker, Chung-Yu Win, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Dependence of Device Structures on Latchup Immunity in a High-Voltage 40-V CMOS Process With Drain-Extended MOSFETs

Ming-Dou Ker, Sheng-Fu Hsu, 2007, IEEE Transactions on Electron Devices.

Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications

Ming-Dou Ker, Chih-Ting Yeh, M. Ker, 2012, Microelectron. Reliab..

TLU in CMOS ICs in the Electrical Fast Transient Test

Ming-Dou Ker, Sheng-Fu Hsu, 2009 .

Optimization of Guard Ring Structures to Improve Latchup Immunity in an 18 V DDDMOS Process

Ming-Dou Ker, Chia-Tsen Dai, M. Ker, 2016, IEEE Transactions on Electron Devices.

Design of Mixed-Voltage-Tolerant Crystal Oscillator Circuit in Low-Voltage CMOS Technology

Ming-Dou Ker, Tzu-Ming Wang, Hung-Tai Liao, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

A new charge pump circuit dealing with gate-oxide reliability issue in low-voltage processes

Chia-Sheng Tsai, Ming-Dou Ker, Shih-Lun Chen, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

SD(Eleetrostatic Discharg e Protection Design foranoeectronics inCMOS ecnolo

Ming-Dou Ker, 2006 .

A High-Voltage-Tolerant and Power-Efficient Stimulator With Adaptive Power Supply Realized in Low-Voltage CMOS Process for Implantable Biomedical Applications

Ming-Dou Ker, Zhicong Luo, M. Ker, 2018, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Overview of on-Chip Stimulator Designs for Biomedical Applications

Ming-Dou Ker, Chun-Yu Lin, M. Ker, 2012 .

Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method. I. theoretical derivation

Chung-Yu Wu, Ming-Dou Ker, Chung-Yu Wu, 1995 .

Layout optimization on low-voltage-triggered PNP devices for ESD protection in mixed-voltage I/O interfaces

Ming-Dou Ker, Wei-Jen Chang, 2004, Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2004 (IEEE Cat. No.04TH8743).

Chip-level and board-level CDM ESD tests on IC products

Ming-Dou Ker, Yuan-Wen Hsiao, Chih-Kuo Huang, 2009, 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Abnormal ESD Damages Occur in Interface Circuits between Different Power Domains in ND-Mode MM ESD Stress

Shih-Hung Chen, Ming-Dou Ker, Che-Hao Chuang, 2006, 2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Novel ESD implantation for sub-quarter-micron CMOS technology with enhanced machine-model ESD robustness

Ming-Dou Ker, Hsin-Chyh Hsu, Jeng-Jie Peng, 2002, Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614).

Design optimization of ESD protection and latchup prevention for a serial I/O IC

Ming-Dou Ker, Jeng-Chou Tseng, Wei-Fang Chen, 2004, Microelectron. Reliab..

Experimental Evaluation and Device Simulation of Device Structure Influences on Latchup Immunity in High-Voltage 40-V CMOS Process

Ming-Dou Ker, Sheng-Fu Hsu, Yeh-Ning Jou, 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

An on-chip ESD protection circuit with complementary SCR structures for submicron CMOS ICs

Chung-Yu Wu, Ming-Dou Ker, Hsin-Chin Jiang, 1994, Proceedings of 1994 37th Midwest Symposium on Circuits and Systems.

On-chip ESD protection design by using polysilicon diodes in CMOS process

Tung-Yang Chen, Chung-Yu Wu, Ming-Dou Ker, 2001 .

Compensation circuit with additional junction sensor to enhance latchup immunity for CMOS integrated circuits

Ming-Dou Ker, Hui-Wen Tsai, 2015, 2015 European Conference on Circuit Theory and Design (ECCTD).

Modeling the positive-feedback regenerative process of CMOS latchup by a positive transient pole method. II. Quantitative evaluation

Chung-Yu Wu, Ming-Dou Ker, Chung-Yu Wu, 1995 .

P‐49: Design of Digital Time‐Modulation Pixel Memory Circuit on Glass Substrate for Low Power Application

Ming-Dou Ker, Tzu-Ming Wang, Szu Han Chen, 2011 .

Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI

Chung-Yu Wu, Ming-Dou Ker, Hun-Hsien Chang, 1996 .

Investigation on safe operating area and ESD robustness in a 60-V BCD process with different deep P-Well test structures

Ming-Dou Ker, Chia-Tsen Dai, 2013, 2013 IEEE International Conference on Microelectronic Test Structures (ICMTS).

Design of high-voltage-tolerant level shifter in low voltage CMOS process for neuro stimulator

Ming-Dou Ker, Zhicong Luo, 2016, 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS).

Transient-to-digital converter for ESD protection design in microelectronic systems

Tung-Yang Chen, Ming-Dou Ker, Cheng-Cheng Yen, 2008, 2008 IEEE Asian Solid-State Circuits Conference.

2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process

Chun-Yu Lin, Ming-Dou Ker, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Optimized layout on ESD protection diode with low parasitic capacitance

Ming-Dou Ker, Chih-Ting Yeh, 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

Impact of Gate Tunneling Leakage on Performances of Phase Locked Loop Circuit in Nanoscale CMOS Technology

Ming-Dou Ker, Jung-Sheng Chen, 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

System-Level ESD Protection for Automotive Electronics by Co-Design of TVS and CAN Transceiver Chips

Ming-Dou Ker, Che-Hao Chuang, 2017, IEEE Transactions on Device and Materials Reliability.

Implantable Stimulator for Epileptic Seizure Suppression With Loading Impedance Adaptability

Chun-Yu Lin, Ming-Dou Ker, Wei-Ling Chen, 2013, IEEE Transactions on Biomedical Circuits and Systems.

Overview on the design of low-leakage power-rail ESD clamp circuits in nanoscale CMOS processes

Ming-Dou Ker, Federico A. Altolaguirre, 2011, 2011 Argentine School of Micro-Nanoelectronics, Technology and Applications.

Substrate-triggered technique for on-chip ESD protection design in a 0.18-/spl mu/m salicided CMOS process

Tung-Yang Chen, Ming-Dou Ker, 2003 .

ESD protection design with stacked low-voltage devices for high-voltage pins of battery-monitoring IC

Ming-Dou Ker, Chia-Tsen Dai, 2015, 2015 28th IEEE International System-on-Chip Conference (SOCC).

Design and In Vivo Verification of a CMOS Bone-Guided Cochlear Implant Microsystem

Chia-Hsiang Yang, Chung-Yu Wu, Ming-Dou Ker, 2019, IEEE Transactions on Biomedical Engineering.

Transient analysis of submicron CMOS latchup with a physical criterion

Chung-Yu Wu, Ming-Dou Ker, Chung-Yu Wu, 1994 .

New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness

Tung-Yang Chen, Ming-Dou Ker, Hun-Hsien Chang, 1999 .

Design of AC-coupled circuit for high-speed interconnects

Yu-Jung Huang, Ming-Dou Ker, Ming-Kun Chen, 2012, 2012 IEEE Global High Tech Congress on Electronics.

Design on new tracking circuit of I/O buffer in 0.13-/spl mu/m cell library for mixed-voltage application

Ming-Dou Ker, Che-Hao Chuang, Zi-Ping Chen, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Design of Mixed-Voltage Crystal Oscillator Circuit in Low-Voltage CMOS Technology

Ming-Dou Ker, Hung-Tai Liao, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits

Ming-Dou Ker, Yuan-Wen Hsiao, 2009, IEICE Trans. Electron..

Mew diode string design with very low leakage current for using in power supply ESD clamp circuits

Ming-Dou Ker, Hun-Hsien Chang, Wen-Yu Lo, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

Design of negative high voltage generator for biphasic stimulator with soc integration consideration

Chun-Yu Lin, Ming-Dou Ker, Ya-Chun Huang, 2012, 2012 IEEE Biomedical Circuits and Systems Conference (BioCAS).

ESD protection designs with lowcapacitance consideration for radiofrequency integrated circuits

Ming-Dou Ker, Chun-Yu Lin, Yuan Wen Hsiao, 2010 .

Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-/spl mu/m CMOS process

Ming-Dou Ker, Kuo-Chun Hsu, 2003 .

Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection

Ming-Dou Ker, Wen-Yi Chen, Yeh-Ning Jou, 2009, 2009 IEEE International Symposium on Circuits and Systems.

Design of on-chip power-rail ESD clamp circuit with ultra-small capacitance to detect ESD transition

Shih-Hung Chen, Ming-Dou Ker, 2009, 2009 International Symposium on VLSI Design, Automation and Test.

Study of board-level noise filters to prevent transient-induced latchup in CMOS integrated circuits during EMC/ESD test

Ming-Dou Ker, Sheng-Fu Hsu, 2006, 2006 17th International Zurich Symposium on Electromagnetic Compatibility.

Test structures to verify ESD robustness of on-glass devices in LTPS technology

Ming-Dou Ker, Chih-Kang Deng, Sheng-Chieh Yang, 2004, Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516).

CMOS on-chip electrostatic discharge protection circuit using four-SCR structures with low ESD-trigger voltage

Chung-Yu Wu, Ming-Dou Ker, 1994 .

ESD protection for CMOS ASIC in noisy environments with high-current low-voltage triggering SCR devices

Ming-Dou Ker, 1997, Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334).

Circuit Performance Degradation of Switched-Capacitor Circuit with Bootstrapped Technique due to Gate-Oxide Overstress in a 130-nm CMOS Process

Ming-Dou Ker, Jung-Sheng Chen, 2008, IEICE Trans. Electron..

Study on ESD protection design with stacked low-voltage devices for high-voltage applications

Ming-Dou Ker, Chia-Tsen Dai, 2014, 2014 IEEE International Reliability Physics Symposium.

Robust ESD Protection Design for 40-Gb/s Transceiver in 65-nm CMOS Process

Chun-Yu Lin, Li-Wei Chu, Ming-Dou Ker, 2013, IEEE Transactions on Electron Devices.

Self-protected LDMOS output device with embedded SCR to improve ESD robustness in 0.25-μm 60-V BCD process

Ming-Dou Ker, Chia-Tsen Dai, Yu-Ching Huang, 2013, 2013 International Symposium on Next-Generation Electronics.

New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC's

Chung-Yu Wu, Ming-Dou Ker, Wen-Yu Lo, 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

ESD Protection Design for Mixed-Voltage I/O Interfaces -- Overview

Ming-Dou Ker, Kun-Hsien Lin, 2005, 2005 IEEE Conference on Electron Devices and Solid-State Circuits.

ESD Protection Design With On-Chip ESD Bus and High-Voltage-Tolerant ESD Clamp Circuit for Mixed-Voltage I/O Buffers

Ming-Dou Ker, Wei-Jen Chang, 2008, IEEE Transactions on Electron Devices.

ESD self-protection design on 2.4-GHz T/R switch for RF application in CMOS process

Chun-Yu Lin, Ming-Dou Ker, Rui-Hong Liu, 2016, 2016 IEEE International Reliability Physics Symposium (IRPS).

Level shifters for high-speed 1 V to 3.3 V interfaces in a 0.13 /spl mu/m Cu-interconnection/low-k CMOS technology

Ming-Dou Ker, Wen-Tai Wang, Mi-Chang Chiang, 2001, 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517).

ESD (Electrostatic Discharge) Protection Design for Nanoelectronics in CMOS Technology

Ming-Dou Ker, 2006, 2006 Advanced Signal Processing, Circuit and System Design Techniques for Communications.

Design on mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applications

Chia-Sheng Tsai, Ming-Dou Ker, Shih-Lun Chen, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Latch-Up Protection Design With Corresponding Complementary Current to Suppress the Effect of External Current Triggers

Ming-Dou Ker, Hui-Wen Tsai, 2015, IEEE Transactions on Device and Materials Reliability.

ESD protection design and verification in a 0.35-/spl mu/m CMOS ASIC library

Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang, 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).

Decreasing-size distributed ESD protection scheme for broad-band RF circuits

Ming-Dou Ker, Bing-Jye Kuo, 2005, IEEE Transactions on Microwave Theory and Techniques.

Design on ESD protection circuit with very low and constant input capacitance

Tung-Yang Chen, Ming-Dou Ker, 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant

Chun-Yu Lin, Ming-Dou Ker, Kuan-Yu Lin, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

An Output Buffer for 3.3-V Applications in a 0.13-$\mu\hbox{m}$ 1/2.5-V CMOS Process

Ming-Dou Ker, Shih-Lun Chen, 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

Design on latchup-free power-rail ESD clamp circuit in high-voltage CMOS ICs

Ming-Dou Ker, Kun-Hsien Lin, 2004, 2004 Electrical Overstress/Electrostatic Discharge Symposium.

Design of 2×VDD-Tolerant I/O Buffer with Considerations of Gate-Oxide Reliability and Hot-Carrier Degradation

Ming-Dou Ker, Hui-Wen Tsai, 2007, 2007 14th IEEE International Conference on Electronics, Circuits and Systems.

Implementation of the cosine law for location awareness system

Yu-Jung Huang, Ming-Dou Ker, Pei-Ju Lin, 2010, 2010 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia).

Investigation of Human-Body-Model and Machine-Model ESD Robustness on Stacked Low-Voltage Field-Oxide Devices for High-Voltage Applications

Ming-Dou Ker, Yi-Jie Huang, 2016, IEEE Transactions on Electron Devices.

Stacked low-voltage PMOS for high-voltage ESD protection with latchup-free immunity

Ming-Dou Ker, Yeh-Ning Jou, Geeng-Lih Lin, 2015, 2015 Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC).

ESD protection design for differential low-noise amplifier with cross-coupled SCR

Chun-Yu Lin, Ming-Dou Ker, Yuan-Wen Hsiao, 2010, 2010 IEEE International Conference on Integrated Circuit Design and Technology.

Design and Realization of Delta-Sigma Analog-to-Digital Converter in LTPS Technology

Ming-Dou Ker, Yu-Hsuan Li, Chun-Huai Li, 2009 .

Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology

Chun-Yu Lin, Ming-Dou Ker, Rong-Kun Chang, 2015, 2015 IEEE 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits.

ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup

Ming-Dou Ker, Wen-Yi Chen, Che-Lun Hsu, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Design on Mixed-Voltage I/O Buffers with Consideration of Hot-Carrier Reliability

Ming-Dou Ker, Fang-Ling Hu, 2007, 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

On-Chip ESD Protection Design for Automotive Vacuum-Fluorescent-Display (VFD) Driver IC to Sustain High ESD Stress

Ming-Dou Ker, Wei-Jen Chang, 2007, IEEE Transactions on Device and Materials Reliability.

Component-Level Measurement for Transient-Induced Latch-up in CMOS ICs Under System-Level ESD Considerations

Ming-Dou Ker, Sheng-Fu Hsu, 2006, IEEE Transactions on Device and Materials Reliability.

On-panel output buffer with offset compensation technique for data driver in LTPS technology

Ming-Dou Ker, Chih-Kang Deng, Ju-Lin Huang, 2006, Journal of Display Technology.

A Latchup-Immune and Robust SCR Device for ESD Protection in 0.25-μm 5-V CMOS Process

Ming-Dou Ker, Yu-Ching Huang, 2013, IEEE Electron Device Letters.

Investigation on device characteristics of MOSFET transistor placed under bond pad for high-pin-count SOC applications

Ming-Dou Ker, Jeng-Jie Peng, 2004 .

Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes

Tung-Yang Chen, Ming-Dou Ker, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test

Ming-Dou Ker, Cheng-Cheng Yen, 2008, IEEE Journal of Solid-State Circuits.

Low-voltage-triggered PNP devices for ESD protection design in mixed-voltage I/O interface with over-VDD and under-VSS signal levels

Ming-Dou Ker, Wen-Yu Lo, Wei-Jen Chang, 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

Investigation on ESD robustness of CMOS devices in a 1.8-V 0.15-/spl mu/m partially-depleted SOI salicide CMOS technology

Tung-Yang Chen, Ming-Dou Ker, S.-S. Chen, 2001, 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517).

A 5-GHz Differential Low-Noise Amplifier With High Pin-to-Pin ESD Robustness in a 130-nm CMOS Process

Ming-Dou Ker, Yuan-Wen Hsiao, 2009, IEEE Transactions on Microwave Theory and Techniques.

Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology

Ming-Dou Ker, Chang-Tzu Wang, 2009, IEEE J. Solid State Circuits.

Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration

Ming-Dou Ker, Wen-Yi Chen, Yeh-Ning Jou, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

Adaptable stimulus driver for epileptic seizure suppression

Chun-Yu Lin, Ming-Dou Ker, Wei-Ling Chen, 2011, 2011 IEEE International Conference on IC Design & Technology.

Source-side engineering to increase holding voltage of LDMOS in a 0.5-m 16-V BCD technology to avoid latch-up failure

Ming-Dou Ker, Wen-Yi Chen, Yeh-Ning Jou, 2009, 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Hardware/firmware co-design in an 8-bits microcontroller to solve the system-level ESD issue on keyboard

Ming-Dou Ker, Yu-Yu Sung, 1999, Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396).

Design of 2.5 V/5 V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuit

Chia-Sheng Tsai, Ming-Dou Ker, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

ESD protection design for radio-frequency integrated circuits in nanoscale CMOS technology

Ming-Hsien Tsai, Chun-Yu Lin, Li-Wei Chu, 2013, 2013 13th IEEE International Conference on Nanotechnology (IEEE-NANO 2013).

Design of 2xVDD-tolerant I/O buffer with 1xVDD CMOS devices

Ming-Dou Ker, Yan-Liang Lin, 2009, 2009 IEEE Custom Integrated Circuits Conference.

lementary- CR ESD Protecti

Chung-Yu Wu, Ming-Dou Ker, Hun-Hsien Chang, 1996 .

Evaluation on board-level noise filter networks to suppress transient-induced latchup in CMOS ICs under system-level ESD test

Ming-Dou Ker, Sheng-Fu Hsu, 2006, IEEE Transactions on Electromagnetic Compatibility.

Design to avoid the over-gate-driven effect on ESD protection circuits in deep-submicron CMOS processes

Ming-Dou Ker, Wen-Yi Chen, 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

New design of transient-noise detection circuit with SCR device for system-level ESD protection

Ming-Dou Ker, Wan-Yen Lin, 2012, 10th IEEE International NEWCAS Conference.

Gate-Oxide Reliability on CMOS Analog Amplifiers in a 130-nm Low-Voltage CMOS Processes

Ming-Dou Ker, Jung-Sheng Chen, 2006, 2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits.

ESD protection for slew-rate-controlled output buffer in a 0.5 μm CMOS SRAM technology

Ming-Dou Ker, Chau-Neng Wu, 1998 .

Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications

Tung-Yang Chen, Chung-Yu Wu, Ming-Dou Ker, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

Low-Leakage and Low-Trigger-Voltage SCR Device for ESD Protection in 28-nm High- $k$ Metal Gate CMOS Process

Ming-Dou Ker, Chun-Yu Lin, Yi-Han Wu, 2016, IEEE Electron Device Letters.

Substrate-triggered ESD clamp devices for use in power-rail ESD clamp circuits

Tung-Yang Chen, Chung-Yu Wu, Ming-Dou Ker, 2002 .

ESD robustness of thin-film devices with different layout structures in LTPS technology

Ming-Dou Ker, Chih-Kang Deng, 2006, Microelectron. Reliab..

2xVDD-tolerant crystal oscillator circuit realized with 1xVDD CMOS devices without gate-oxide reliability issue

Ming-Dou Ker, Tzu-Ming Wang, Hung-Tai Liao, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Physical mechanism and device simulation on transient-induced latchup in CMOS ICs under system-level ESD test

Ming-Dou Ker, Sheng-Fu Hsu, 2005 .

New Curvature-Compensation Technique for CMOS Bandgap Reference With Sub-1-V Operation

Ming-Dou Ker, Jung-Sheng Chen, Ching-Yun Chu, 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

Electrostatic discharge (ESD) protection for CMOS output buffers in scaled-down VLSI technology

Ming-Dou Ker, 1998 .

New matching methodology of low-noise amplifier with ESD protection

Ming-Dou Ker, Bo-Shih Huang, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Overview and Design of Mixed-Voltage I/O Buffers With Low-Voltage Thin-Oxide CMOS Transistors

Chia-Sheng Tsai, Ming-Dou Ker, Shih-Lun Chen, 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

Transient-induced latchup in CMOS technology: physical mechanism and device simulation

Ming-Dou Ker, Sheng-Fu Hsu, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

On-Chip ESD detection circuit for system-level ESD protection design

Tung-Yang Chen, Ming-Dou Ker, Wan-Yen Lin, 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

Layout design on bond pads to improve the firmness of bond wire in packaged IC products

Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang, 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).

ESD protection design with lateral DMOS transistor in 40-V BCD technology

Ming-Dou Ker, Tien-Hao Tang, Kuan-Cheng Su, 2010, 2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Investigation of the gate-driven effect and substrate-triggered effect on ESD robustness of CMOS devices

Tung-Yang Chen, Ming-Dou Ker, 2001 .

Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process

Ming-Dou Ker, Chih-Ting Yeh, 2013, 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT).

Design on mixed-voltage I/O buffers with slew-rate control in low-voltage CMOS process

Ming-Dou Ker, Tzu-Ming Wang, Fang-Ling Hu, 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

Ultra-High-Voltage Charge Pump Circuit in Low-Voltage Bulk CMOS Processes With Polysilicon Diodes

Ming-Dou Ker, Shih-Lun Chen, M. Ker, 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs

Chung-Yu Wu, Ming-Dou Ker, Hun-Hsien Chang, 1997 .

Whole-chip ESD protection strategy for CMOS IC's with multiple mixed-voltage power pins

Ming-Dou Ker, Hun-Hsien Chang, 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).

SCR device with dynamic holding voltage for on-chip ESD protection in a 0.25-/spl mu/m fully salicided CMOS process

Ming-Dou Ker, Zi-Ping Chen, 2004 .

Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-/spl mu/m CMOS technology

Ming-Dou Ker, Che-Hao Chuang, M. Ker, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology

Shih-Hung Chen, Ming-Dou Ker, 2006, Microelectron. Reliab..

Design of differential low-noise amplifier with cross-coupled-SCR ESD protection scheme

Chun-Yu Lin, Ming-Dou Ker, Yuan-Wen Hsiao, 2010, Microelectron. Reliab..

Self-Reset Transient Detection Circuit for On-Chip Protection Against System-Level Electrical-Transient Disturbance

Ming-Dou Ker, Xiao-Rui Kang, 2018, IEEE Transactions on Device and Materials Reliability.

Low-Capacitance and Fast Turn-on SCR for RF ESD Protection

Chun-Yu Lin, Ming-Dou Ker, Guo-Xuan Meng, 2008, IEICE Trans. Electron..

Circuit design to achieve whole-chip ESD protection for UXGA/HDTV LCOS IC product

Shih-Hung Chen, Ming-Dou Ker, Tang-Kui Tseng, 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

The Impact of Inner Pickup on ESD Robustness of Multi-Finger NMOS in Nanoscale CMOS Technology

Ming-Dou Ker, Hsin-Chyh Hsu, 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's

Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang, 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

Layout verification to improve ESD/latchup immunity of scaled-down CMOS cell libraries

Ming-Dou Ker, Jiann-Horng Lin, Sue-Mei Hsiao, 1997, Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334).

Latchup test-induced failure within ESD protection diodes in a high-voltage CMOS IC product

Ming-Dou Ker, Jen-Chou Tseng, Chia-Ku Tsai, 2004, 2004 Electrical Overstress/Electrostatic Discharge Symposium.

Design of 2.4-GHz T/R switch with embedded ESD protection devices in CMOS process

Chun-Yu Lin, Ming-Dou Ker, Rui-Hong Liu, 2017, Microelectron. Reliab..

ESD Protection Design of High-Linearity SPDT CMOS T/R Switch for Cellular Applications

Ming-Dou Ker, Tao-Yi Hung, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

Large-Swing-Tolerant ESD Protection Circuit for Gigahertz Power Amplifier in a 65-nm CMOS Process

Chun-Yu Lin, Li-Wei Chu, Ming-Dou Ker, 2013, IEEE Transactions on Microwave Theory and Techniques.

CMOS Power Amplifier with ESD Protection Design Merged in Matching Network

Ming-Dou Ker, Bo-Shih Huang, Yu-Da Shiu, 2007, 2007 14th IEEE International Conference on Electronics, Circuits and Systems.

Regulated Charge Pump With New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process

Ming-Dou Ker, Wan-Hsueh Cheng, Ting-Yang Yen, 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

ESD protection design for mixed-voltage-tolerant I/O buffers with substrate-triggered technique

Ming-Dou Ker, Hsin-Chyh Hsu, 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

The Effect of IEC-Like Fast Transients on $RC$ -Triggered ESD Power Clamps

Ming-Dou Ker, Cheng-Cheng Yen, 2009, IEEE Transactions on Electron Devices.

ESD protection design with lateral DMOS transistor in 40-V BCD technology

Ming-Dou Ker, Tien-Hao Tang, Kuan-Cheng Su, 2010, IPFA 2010.

A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control

Sheng-Fu Liang, Chia-Hsiang Yang, Chun-Yu Lin, 2013, IEEE Journal of Solid-State Circuits.

ESD protection design with latchup-free immunity in 120V SOI process

Ming-Dou Ker, Yeh-Ning Jou, Geeng-Lih Lin, 2015, 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Impact of MOSFET gate-oxide reliability on CMOS operational amplifiers in a 130-nm low-voltage CMOS process

Ming-Dou Ker, Jung-Sheng Chen, 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process

Ming-Dou Ker, Wen-Yi Chen, Kuo-Chun Hsu, 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation

Ming-Dou Ker, Jung-Sheng Chen, 2005, 2005 IEEE International Symposium on Circuits and Systems.

SCR device fabricated with dummy-gate structure to improve turn-on speed for effective ESD protection in CMOS technology

Ming-Dou Ker, Kuo-Chun Hsu, 2005 .

Investigation of Unexpected Latchup Path Between HV-LDMOS and LV-CMOS in a 0.25- $\mu \text{m}$ 60-V/5-V BCD Technology

Ming-Dou Ker, Chia-Tsen Dai, M. Ker, 2017, IEEE Transactions on Electron Devices.

On-panel analog output buffer for data driver with consideration of device characteristic variation in LTPS technology

Ming-Dou Ker, Chun-Yao Huang, Yu-Hsuan Li, 2007 .

New 4-Bit Transient-to-Digital Converter for System-Level ESD Protection in Display Panels

Ming-Dou Ker, Cheng-Cheng Yen, 2012, IEEE Transactions on Industrial Electronics.

Special Layout Issues for Latchup Prevention

Ming-Dou Ker, Sheng-Fu Hsu, 2009 .

P‐45: On‐Chip ESD Protection Design for UXGA/HDTV LCoS in 0.35‐μm CMOS Technology

Shih-Hung Chen, Ming-Dou Ker, Tang-Kui Tseng, 2004 .

Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOC IC's

Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang, 2003, International Conference on Microelectronic Test Structures, 2003..

Whole-chip ESD protection design for submicron CMOS VLSI

Ming-Dou Ker, Shue-Chang Liu, 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

Efficient Output Esd Protection Of High-speed Sram Ic With Well-coupled Technique In Sub-pm Cmos Technology

Ming-Dou Ker, Chau-Neng Wu, Ta-Lee Yu, 1997, Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications.

Transient-Induced Latchup in CMOS ICs Under Electrical Fast-Transient Test

Tung-Yang Chen, Ming-Dou Ker, Cheng-Cheng Yen, 2009, IEEE Transactions on Device and Materials Reliability.

Analysis and Prevention on NC-ball induced ESD Damages in a 683-Pin BGA Packaged Chipset IC

Ming-Dou Ker, Wen-Yu Lo, 2003, Microelectron. Reliab..

Efficient output ESD protection for 0.5-/spl mu/m high-speed CMOS SRAM IC with well-coupled technique

Ming-Dou Ker, Chau-Neng Wu, 1996 .

Optimization on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-μm CMOS technology

Shih-Hung Chen, Ming-Dou Ker, 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

Implementation of Initial-On ESD Protection Concept With PMOS-Triggered SCR Devices in Deep-Submicron CMOS Technology

Shih-Hung Chen, Ming-Dou Ker, 2007, IEEE Journal of Solid-State Circuits.

P-17: On-Panel Design Technique of Threshold Voltage Compensation for Output Buffer in LTPS Technology

Ming-Dou Ker, Chih-Kang Deng, Ju-Lin Huang, 2005 .

ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications

Tung-Yang Chen, Chung-Yu Wu, Ming-Dou Ker, 2000, IEEE Journal of Solid-State Circuits.

Substrate-triggered ESD protection circuit without extra process modification

Tung-Yang Chen, Ming-Dou Ker, M. Ker, 2003 .

Design to suppress return-back leakage current of charge pump circuit in low-voltage CMOS process

Ming-Dou Ker, Yi-Hsin Weng, Hui-Wen Tsai, 2011, Microelectron. Reliab..

ESD Protection Design for CMOS Integrated Circuits with Mixed-Voltage I/O Interfaces

Ming-Dou Ker, Wei-Jen Chang, 2006, 2006 Ph.D. Research in Microelectronics and Electronics.

Optimization on Layout Style of ESD Protection Diode for Radio-Frequency Front-End and High-Speed I/O Interface Circuits

Ming-Dou Ker, Yung-Chih Liang, Chih-Ting Yeh, 2010, IEEE Transactions on Device and Materials Reliability.

Self-Substrate-Triggered Technique to Enhance Turn-On Uniformity of Multi-Finger ESD Protection Devices

Ming-Dou Ker, Jia-Huei Chen, 2006, IEEE Journal of Solid-State Circuits.

ESD Protection Design With Low-Capacitance Consideration for High-Speed/High-Frequency I/O Interfaces in Integrated Circuits

Ming-Dou Ker, Yuan-Wen Hsiao, M. Ker, 2007 .

Layout Consideration and Circuit Solution to Prevent EOS Failure Induced by Latchup Test in a High-Voltage Integrated Circuits

Ming-Dou Ker, Hui-Wen Tsai, 2014, IEEE Transactions on Device and Materials Reliability.

ESD Robustness of 40-V CMOS Devices With/Without Drift Implant

Ming-Dou Ker, Tien-Hao Tang, Kuan-Cheng Su, 2006, 2006 IEEE International Integrated Reliability Workshop Final Report.

Modeling the parasitic capacitance of ESD protection SCR to co-design matching network in RF ICs

Chun-Yu Lin, Ming-Dou Ker, 2010, 2010 International Symposium on Next Generation Electronics.

Bond Pad Design With Low Capacitance in CMOS Technology for RF Applications

Ming-Dou Ker, Yuan-Wen Hsiao, 2007, IEEE Electron Device Letters.

On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology

Ming-Dou Ker, Chun-Yu Lin, Jie-Ting Chen, 2017, IEEE Transactions on Electron Devices.

Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product

Ming-Dou Ker, I-Cheng Lin, Chih-Yao Huang, 2003, Microelectron. Reliab..

Investigation on CDM ESD events at core circuits in a 65-nm CMOS process

Chun-Yu Lin, Ming-Dou Ker, Tang-Long Chang, 2012, Microelectron. Reliab..

CMOS output buffer with an ESD protection circuit

Ming-Dou Ker, Tain-Shun Wu, 1995 .

Transient-to-digital converter for protection design in CMOS integrated circuits against electrical fast transient

Tung-Yang Chen, Ming-Dou Ker, Cheng-Cheng Yen, 2009, 2009 IEEE International Symposium on Electromagnetic Compatibility.

Surge protection design with surge-to-digital converter for microelectronic circuits and systems

Ming-Dou Ker, Wen-Chieh Chen, 2018, Microelectron. Reliab..

ESD-induced latchup-like failure in a touch panel control IC

Ming-Dou Ker, Wuu-Trong Shieh, Po-Yen Chiu, 2017, 2017 IEEE 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).

CORDIC implementation of RSSI localization method

Yu-Jung Huang, Ming-Dou Ker, Pei-Ju Lin, 2010, 2010 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia).

CDM ESD protection in CMOS integrated circuits

Ming-Dou Ker, Yuan-Wen Hsiao, 2008, 2008 Argentine School of Micro-Nanoelectronics, Technology and Applications.

Design on ESD protection scheme for IC with power-down-mode operation

Ming-Dou Ker, Kun-Hsien Lin, 2004 .

ESD protection design for 1- to 10-GHz distributed amplifier in CMOS technology

Ming-Dou Ker, Yuan-Wen Hsiao, Bing-Jye Kuo, 2005 .

Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology

Ming-Dou Ker, Tien-Hao Tang, Kuan-Cheng Su, 2009, 2009 IEEE International Conference on IC Design and Technology.

Methodology on Extracting Compact Layout Rules for Latchup Prevention

Ming-Dou Ker, Sheng-Fu Hsu, 2009 .

Digital time‐modulation pixel memory circuit in LTPS technology

Ming-Dou Ker, Tzu-Ming Wang, Szu-Han Chen, 2011 .

Test Structure on SCR Device in Waffle Layout for RF ESD Protection

Chun-Yu Lin, Ming-Dou Ker, 2007, 2007 IEEE International Conference on Microelectronic Test Structures.

Electrostatic discharge protection scheme without leakage current path for CMOS IC operating in power-down-mode condition on a system board

Ming-Dou Ker, Kun-Hsien Lin, 2006, Microelectron. Reliab..

Power-Rail ESD Clamp Circuit With Ultralow Standby Leakage Current and High Area Efficiency in Nanometer CMOS Technology

Ming-Dou Ker, Chih-Ting Yeh, 2012, IEEE Transactions on Electron Devices.

Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology

Ming-Dou Ker, Po-Yen Chiu, 2013, 2013 IEEE International SOC Conference.

Self-substrate-triggered technique to enhance turn-on uniformity of multi-finger ESD protection devices

Ming-Dou Ker, Jia-Huei Chen, Kuo-Chun Hsu, 2006, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..

ESD Protection Design for 60-GHz LNA With Inductor-Triggered SCR in 65-nm CMOS Process

Chun-Yu Lin, Li-Wei Chu, Ming-Dou Ker, 2012, IEEE Transactions on Microwave Theory and Techniques.

Low-Leakage Bidirectional SCR With Symmetrical Trigger Circuit for ESD Protection in 40-nm CMOS Process

Ming-Dou Ker, Federico A. Altolaguirre, 2016, IEEE Transactions on Device and Materials Reliability.

On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process

Ming-Dou Ker, Kuo-Chun Hsu, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Interference of ESD protection diodes on RF performance in Giga-Hz RF circuits

Ming-Dou Ker, Chien-Ming Lee, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

High-Voltage-Tolerant ESD Clamp Circuit With Low Standby Leakage in Nanoscale CMOS Process

Chun-Yu Lin, Ming-Dou Ker, 2010, IEEE Transactions on Electron Devices.

Resistor-less power-rail ESD clamp circuit with ultra-low leakage current in 65nm CMOS process

Ming-Dou Ker, Chih-Ting Yeh, 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

Whole-chip ESD protection strategy for CMOS integrated circuits in nanotechnology

Ming-Dou Ker, Hsin-Chin Jiang, 2001, Proceedings of the 2001 1st IEEE Conference on Nanotechnology. IEEE-NANO 2001 (Cat. No.01EX516).

FOR TRANSIENT-JNDUCED LATCHUP WITH BI-POLAR TRIGGER

Ming-Dou Ker, Sheng-Fu Hsu, 2005 .

Transient-Induced Latchup Dependence on Power-Pin Damping Frequency and Damping Factor in CMOS Integrated Circuits

Ming-Dou Ker, Sheng-Fu Hsu, 2007, IEEE Transactions on Electron Devices.

ESD Protection for Mixed-Voltage I/O in LowVoltage Thin-Oxide CMOS

Ming-Dou Ker, Wen-Yi Chen, Wei-Jen Chang, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

Area-Efficient ESD Clamp Circuit With a Capacitance-Boosting Technique to Minimize Standby Leakage Current

Ming-Dou Ker, Federico A. Altolaguirre, 2015, IEEE Transactions on Device and Materials Reliability.

ESD protection design for IC with power-down-mode operation

Ming-Dou Ker, Kun-Hsien Lin, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Design of stimulus driver to suppress epileptic seizure with adaptive loading consideration

Chun-Yu Lin, Ming-Dou Ker, Wei-Ling Chen, 2010, 2010 International Symposium on Next Generation Electronics.

Optimization of broadband RF performance and ESD robustness by π-model distributed ESD protection scheme

Ming-Dou Ker, Bing-Jye Kuo, 2004, 2004 Electrical Overstress/Electrostatic Discharge Symposium.

Implementation of delta-sigma analog-to-digital converter in LTPS process

Ming-Dou Ker, Tzu-Ming Wang, Chia-Chi Tsai, 2010 .

ESD Protection Design With Stacked High-Holding-Voltage SCR for High-Voltage Pins in a Battery-Monitoring IC

Ming-Dou Ker, Chia-Tsen Dai, 2016, IEEE Transactions on Electron Devices.

Methodology to Evaluate the Robustness of Integrated Circuits under Cable Discharge Event

Ming-Dou Ker, Tai-Xiang Lai, 2005, 2005 IEEE Conference on Electron Devices and Solid-State Circuits.

Power-rail ESD clamp circuit with embedded-trigger SCR device in a 65-nm CMOS process

Ming-Dou Ker, Federico A. Altolaguirre, 2014, 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS).

Design of 2$\times$VDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology

Ming-Dou Ker, Chang-Tzu Wang, 2010, IEEE Transactions on Electron Devices.

Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process

Ming-Dou Ker, Wen-Yi Chen, Kuo-Chun Hsu, 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

New Design of 2 $\times$ VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology

Ming-Dou Ker, Chih-Ting Yeh, 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology

Ming-Dou Ker, Federico A. Altolaguirre, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

Transient-Induced Latchup in CMOS Integrated Circuits due to Electrical Fast Transient (EFT) Test

Ming-Dou Ker, Cheng-Cheng Yen, 2007, 2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits.

ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process

Yuh-Kuang Tseng, Ming-Dou Ker, Chun Huang, 2007, SoCC.

Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation

Ming-Dou Ker, Hui-Wen Tsai, 2010, Microelectron. Reliab..

Impact of Gate Leakage on Performances of Phase-Locked Loop Circuit in Nanoscale CMOS Technology

Ming-Dou Ker, Jung-Sheng Chen, 2009, IEEE Transactions on Electron Devices.

Failure of On-Chip Power-Rail ESD Clamp Circuits During System-Level ESD Test

Ming-Dou Ker, Cheng-Cheng Yen, 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS ICs

Ming-Dou Ker, Cheng-Cheng Yen, Pi-Chia Shih, 2006, IEEE Custom Integrated Circuits Conference 2006.

Quad-SCR Device for Cross-Domain ESD Protection

Ming-Dou Ker, Federico A. Altolaguirre, 2016, IEEE Transactions on Electron Devices.

An Ultra-Low Voltage CMOS Voltage Controlled Oscillator with Process and Temperature Compensation

Ming-Dou Ker, Ting-Chou Lu, Hsiao-Wen Zan, 2017, IEICE Trans. Electron..

ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins

Ming-Dou Ker, Chyh-Yih Chang, Yi-Shu Chang, 2002, 15th Annual IEEE International ASIC/SOC Conference.

Design of high-voltage-tolerant stimulus driver with adaptive loading consideration to suppress epileptic seizure in a 0.18-μm CMOS process

Ming-Dou Ker, Chun-Yu Lin, Yi Ju Li, 2014 .

ESD protection design for broadband RF circuits with decreasing-size distributed protection scheme

Ming-Dou Ker, Bing-Jye Kuo, 2004, 2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers.

Hardware/firmware co-design in an 8-bits microcontroller to solve the system-level ESD issue on keyboard

Ming-Dou Ker, Yu-Yu Sung, 1999 .

Complementary substrate-triggered SCR devices for on-chip ESD protection circuits

Ming-Dou Ker, Kuo-Chun Hsu, 2002, 15th Annual IEEE International ASIC/SOC Conference.

Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology

Ming-Dou Ker, Jeng-Jie Peng, 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI

Chung-Yu Wu, Ming-Dou Ker, Chung-Yuan Lee, 1992 .

Area-efficient CMOS output buffer with enhanced high ESD reliability for deep submicron CMOS ASIC

Ming-Dou Ker, Yuan-Hua Chu, Tain-Shun Wu, 1995, Proceedings of Eighth International Application Specific Integrated Circuits Conference.

Abnormal ESDDamagesOccurinInterface Circuits between Different PowerDomainsinND-ModeMM ESDStress

Shih-Hung Chen, Ming-Dou Ker, Hsiang-Pin Hung, 2006 .

Dynamic-floating-gate design for output ESD protection in a 0.35-/spl mu/m CMOS cell library

Ming-Dou Ker, Hun-Hsien Chang, Chen-Chia Wang, 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

Automation of Synchronous Bias Transmission Line Pulsing System

Ming-Dou Ker, Hsin-Chyh Hsu, Bor-Wei Chang, 2007, 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

ESD failure mechanisms of analog I/O cells in 0.18-/spl mu/m CMOS technology

Shih-Hung Chen, Ming-Dou Ker, Che-Hao Chuang, 2006 .

A CMOS bandgap reference circuit for sub-1-V operation without using extra low-threshold-voltage device

Ming-Dou Ker, Jung-Sheng Chen, Ching-Yun Chu, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Whole-chip ESD protection for CMOS VLSI/ULSI with multiple power pins

Chung-Yu Wu, Ming-Dou Ker, Tao Cheng, 1994, Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS).

On-chip detection circuit for protection design in display panel against electrical fast transient (EFT) disturbance

Tung-Yang Chen, Ming-Dou Ker, Cheng-Cheng Yen, 2011 .

Layout design to minimize voltage-dependent variation on input capacitance of an analog ESD protection circuit

Tung-Yang Chen, Ming-Dou Ker, 2002 .

An 82.9%-Efficiency Triple-Output Battery Management Unit for Implantable Neuron Stimulator in 180-nm Standard CMOS

Chung-Yu Wu, Ming-Dou Ker, Po-Hung Chen, 2019, IEEE Transactions on Circuits and Systems II: Express Briefs.

Improving Safe Operating Area of nLDMOS Array With Embedded Silicon Controlled Rectifier for ESD Protection in a 24-V BCD Process

Ming-Dou Ker, Wen-Yi Chen, M. Ker, 2011, IEEE Transactions on Electron Devices.

Investigation on Robustness of CMOS Devices Against Cable Discharge Event (CDE) Under Different Layout Parameters in a Deep-Submicrometer CMOS Technology

Ming-Dou Ker, Tai-Hsiang Lai, 2008, IEEE Transactions on Electromagnetic Compatibility.

Dependence of Layout Parameters on CDE (Cable Discharge Event) Robustness of CMOS Devices in a 0.25-μm Salicided CMOS Process

Ming-Dou Ker, Tai-Xiang Lai, 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

SCR device for on-chip ESD protection in RF power amplifier

Chun-Yu Lin, Ming-Dou Ker, 2013, 2013 IEEE International Conference of Electron Devices and Solid-state Circuits.

ESD-transient detection circuit with equivalent capacitance-coupling detection mechanism and high efficiency of layout area in a 65nm CMOS technology

Ming-Dou Ker, Chih-Ting Yeh, 2013, 2013 35th Electrical Overstress/Electrostatic Discharge Symposium.

SCR-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance

Ming-Dou Ker, Wan-Yen Lin, Cheng-Cheng Yen, 2014, Microelectron. Reliab..

51.3: Successful Electrostatic Discharge Protection Design for LTPS Circuits Integrated on Panel

Ming-Dou Ker, Yaw-Ming Tsai, Sheng-Chieh Yang, 2003 .

Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC

Chung-Yu Wu, Ming-Dou Ker, Tao Cheng, 1996, IEEE Trans. Very Large Scale Integr. Syst..

Design on LVDS receiver with new delay-selecting technique for UXGA flat panel display applications

Ming-Dou Ker, Chien-Hua Wu, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-/spl mu/m salicided CMOS process

Ming-Dou Ker, Che-Hao Chuang, Wen-Yu Lo, 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

CMOS on-chip ESD protection design with substrate-triggering technique

Tung-Yang Chen, Chung-Yu Wu, Ming-Dou Ker, 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

A fully integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure control

Chih-Wei Chang, Sheng-Fu Liang, Chun-Yu Lin, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

Mixed-voltage I/O buffer with dynamic gate-bias circuit to achieve 3/spl times/V/sub DD/ input tolerance by using 1/spl times/V/sub DD/ devices and single V/sub DD/ supply

Ming-Dou Ker, Shih-Lun Chen, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

Electrostatic discharge implantation to improve machine-model ESD robustness of stacked NMOS in mixed I/O interface circuits

Ming-Dou Ker, Hsin-Chyh Hsu, Jeng-Jie Peng, 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

On-Chip Transient Voltage Suppressor Integrated With Silicon-Based Transceiver IC for System-Level ESD Protection

Ming-Dou Ker, Che-Hao Chuang, 2014, IEEE Transactions on Industrial Electronics.

Design of Stage-Selective Negative Voltage Generator to Improve On-Chip Power Conversion Efficiency for Neuron Stimulation

Ming-Dou Ker, Shiau-Pin Lin, M. Ker, 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

Self-matched ESD cell in CMOS technology for 60-GHz broadband RF applications

Chun-Yu Lin, Li-Wei Chu, Ming-Dou Ker, 2010, 2010 IEEE Radio Frequency Integrated Circuits Symposium.

Impact of MOSFET Gate-Oxide Reliability on CMOS Operational Amplifier in a 130-nm Low-Voltage Process

Ming-Dou Ker, Jung-Sheng Chen, 2008, IEEE Transactions on Device and Materials Reliability.

A 8 Phases 192MHz Crystal-Less Clock Generator with PVT Calibration

Ming-Dou Ker, Jen-Chieh Liu, Yu Lee, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Design of dynamic-floating-gate technique for output ESD protection in deep-submicron CMOS technology

Ming-Dou Ker, Hun-Hsien Chang, Jiin-Chuan Wu, 1999 .

New transient detection circuit to detect ESD-induced disturbance for automatic recovery design in display panels

Tung-Yang Chen, Ming-Dou Ker, Wan-Yen Lin, 2011, 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Latchup-Like Failure of Power-Rail ESD Clamp Circuits in CMOS Integrated Circuits Under System-Level ESD Test

Ming-Dou Ker, Cheng-Cheng Yen, 2007, 2007 IEEE International Symposium on Electromagnetic Compatibility.

Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS process

Tung-Yang Chen, Ming-Dou Ker, 2003 .

Novel cascode NCLSCR/PCLSCR design with tunable holding voltage for safe whole-chip ESD protection

Ming-Dou Ker, Hun-Hsien Chang, 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

Layout optimization on ESD diodes for giga-Hz RF and high-speed I/O circuits

Ming-Dou Ker, Yung-Chih Liang, Chih-Ting Yeh, 2010, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test.

Layout styles to improve CDM ESD robustness of integrated circuits in 65-nm CMOS process

Chun-Yu Lin, Ming-Dou Ker, Tang-Long Chang, 2011, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test.

ESD protection design for fully integrated CMOS RF power amplifiers with waffle-structured SCR

Chun-Yu Lin, Ming-Dou Ker, Guo-Xuan Meng, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Local CDM ESD Protection Circuits for Cross-Power Domains in 3D IC Applications

Mirko Scholz, Shih-Hung Chen, Dimitri Linten, 2014, IEEE Transactions on Device and Materials Reliability.

Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's

Chung-Yu Wu, Ming-Dou Ker, Tao Cheng, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

Initial-On ESD Protection Design with PMOS-Triggered SCR Device

Shih-Hung Chen, Ming-Dou Ker, 2005, 2005 IEEE Asian Solid-State Circuits Conference.

Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS

Ming-Dou Ker, Chang-Tzu Wang, 2009, 2009 IEEE Custom Integrated Circuits Conference.

Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process

Chun-Yu Lin, Li-Wei Chu, Ming-Dou Ker, 2011, Microelectron. Reliab..

Design of charge pump circuit in low-voltage CMOS process with suppressed return-back leakage current

Ming-Dou Ker, Yi-Hsin Weng, Hui-Wen Tsai, 2010, 2010 IEEE International Conference on Integrated Circuit Design and Technology.

On-chip ESD protection designs in RF integrated circuits for radio and wireless applications

Chun-Yu Lin, Ming-Dou Ker, 2013, 2013 IEEE International Conference of Electron Devices and Solid-state Circuits.

A Digitally Dynamic Power Supply Technique for 16-Channel 12 V-Tolerant Stimulator Realized in a 0.18- μm 1.8-V/3.3-V Low-Voltage CMOS Process

Ming-Dou Ker, Tzu-Yi Yang, Wan-Hsueh Cheng, 2017, IEEE Transactions on Biomedical Circuits and Systems.

Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-blocking mask

Ming-Dou Ker, Hsin-Chyh Hsu, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Active ESD shunt with transistor feedback to reduce latchup susceptibility or false triggering

Ming-Dou Ker, Ping Ping Xu, Paul C. F. Tong, 2004 .

Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs

Shih-Hung Chen, Ming-Dou Ker, 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology

Ming-Hsien Tsai, Chun-Yu Lin, Li-Wei Chu, 2012, 2012 IEEE International Symposium on Circuits and Systems.

Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes

Ming-Dou Ker, Shih-Lun Chen, Chia-Shen Tsai, 2006, IEEE J. Solid State Circuits.

A new Schmitt trigger circuit in a 0.13 /spl mu/m 1/2.5 V CMOS process to receive 3.3 V input signals

Ming-Dou Ker, Shih-Lun Chen, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Active Guard Ring to Improve Latch-Up Immunity

Ming-Dou Ker, Hui-Wen Tsai, 2014, IEEE Transactions on Electron Devices.

Method to evaluate cable discharge event (CDE) reliability of integrated circuits in CMOS technology

Ming-Dou Ker, Tai-Xiang Lai, M. Ker, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

A fully integrated closed-loop neuromodulation SoC with wireless power and bi-directional data telemetry for real-time human epileptic seizure control

Sheng-Fu Liang, Chung-Yu Wu, Ming-Dou Ker, 2017, 2017 Symposium on VLSI Circuits.

ESD protection design on analog pin with very low input capacitance for RF or current-mode applications

Tung-Yang Chen, Chung-Yu Wu, Ming-Dou Ker, 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).

Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits

Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

ESD protection design for wideband RF applications in 65-nm CMOS process

Ming-Hsien Tsai, Chun-Yu Lin, Li-Wei Chu, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Appendix A: Practical ApplicationExtractions of Latchup Design Rules in a 0.18m 1.8 V/3.3V Silicided CMOS Process

Ming-Dou Ker, Sheng-Fu Hsu, 2009 .

Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits

Shih-Hung Chen, Ming-Dou Ker, 2007, Microelectron. Reliab..

ESD protection circuits with novel MOS-bounded diode structures

Ming-Dou Ker, Che-Hao Chuang, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Transient detection circuit for system-level ESD protection and its on-board behavior with EMI/EMC filters

Ming-Dou Ker, Cheng-Cheng Yen, Chi-Sheng Liao, 2008, 2008 IEEE International Symposium on Electromagnetic Compatibility.

Transient-Induced Latchup in CMOS Integrated Circuits

Ming-Dou Ker, Sheng-Fu Hsu, 2009 .

ESD test methods on integrated circuits: an overview

Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang, 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

ESD protection design for RF circuits in CMOS technology with low-c implementation

Ming-Dou Ker, Chun-Yu Lin, 2008 .

Ultra Low-Capacitance Bond Pad for RF Applications in CMOS Technology

Ming-Dou Ker, Yuan-Wen Hsiao, M. Ker, 2007, 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium.

ESD protection design for giga-Hz RF CMOS LNA with novel impedance-isolation technique

Ming-Dou Ker, Chien-Ming Lee, 2003, 2003 Electrical Overstress/Electrostatic Discharge Symposium.

Design of Compact ESD Protection Circuit for V-Band RF Applications in a 65-nm CMOS Technology

Chun-Yu Lin, Li-Wei Chu, Ming-Dou Ker, 2012, IEEE Transactions on Device and Materials Reliability.

ESD protection structure with embedded high-voltage p-type SCR for automotive vacuum-fluorescent-display (VFD) applications

Ming-Dou Ker, Cheng-Chung Chen, Wuu-Trong Shieh, 2005, Proceedings of the 12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005..

Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-/spl mu/m CMOS integrated circuits

Ming-Dou Ker, Kuo-Chun Hsu, 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

High Area-Efficient ESD Clamp Circuit With Equivalent $RC$-Based Detection Mechanism in a 65-nm CMOS Process

Ming-Dou Ker, Chih-Ting Yeh, 2013, IEEE Transactions on Electron Devices.

Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers

Ming-Dou Ker, Chien-Hui Chuang, 2002 .

Miniaturized Intracerebral Potential Recorder for Long-Term Local Field Potential of Deep Brain Signals

Ming-Dou Ker, Chen-Yi Lee, Yi-Huan Ou-Yang, 2020, 2020 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC).

On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS Integrated Circuits to Meet Electromagnetic Compatibility Regulation

Ming-Dou Ker, Cheng-Cheng Yen, Pi-Chia Shih, 2008, IEEE Transactions on Electromagnetic Compatibility.

ESD protection design of low-voltage-triggered p-n-p devices and their failure modes in mixed-voltage I/O interfaces with signal levels higher than VDD and lower than VSS

Ming-Dou Ker, Wei-Jen Chang, 2005 .

The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs

Ming-Dou Ker, Kun-Hsien Lin, 2005 .

Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology

Shih-Hung Chen, Ming-Dou Ker, 2007, 2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Electrostatic discharge protection circuits in CMOS ICs using the lateral SCR devices: an overview

Ming-Dou Ker, 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

Active ESD protection for input transistors in a 40-nm CMOS process

Ming-Dou Ker, Federico A. Altolaguirre, 2015, VLSI Design, Automation and Test(VLSI-DAT).

A new failure mechanism on analog I/O cell under ND-mode ESD stress in deep-submicron CMOS technology

Shih-Hung Chen, Ming-Dou Ker, Che-Hao Chuang, 2005, Proceedings of the 12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005..

New Layout Arrangement to Improve ESD Robustness of Large-Array High-Voltage nLDMOS

Ming-Dou Ker, Wen-Yi Chen, 2010, IEEE Electron Device Letters.

Unexpected failure in power-rail ESD clamp circuits of CMOS integrated circuits in microelectronics systems during electrical fast transient (EFT) test and the re-design solution

Ming-Dou Ker, Cheng-Cheng Yen, 2007, EMC 2007.

Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection

Shih-Hung Chen, Ming-Dou Ker, 2009, IEEE Transactions on Electron Devices.

New Transient Detection Circuit for On-Chip Protection Design Against System-Level Electrical-Transient Disturbance

Ming-Dou Ker, Cheng-Cheng Yen, 2010, IEEE Transactions on Industrial Electronics.

Active ESD Protection Design for Interface Circuits Between Separated Power Domains Against Cross-Power-Domain ESD Stresses

Shih-Hung Chen, Ming-Dou Ker, Hsiang-Pin Hung, 2008, IEEE Transactions on Device and Materials Reliability.

Design of Multi-Channel Monopolar Biphasic Stimulator for Implantable Biomedical Applications

Ming-Dou Ker, Chia-Chi Hsieh, M. Ker, 2018, 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS).

Optimization on SCR device with low capacitance for on-chip ESD protection in UWB RF circuits

Chun-Yu Lin, Ming-Dou Ker, 2008, 2008 15th International Symposium on the Physical and Failure Analysis of Integrated Circuits.

New Ballasting Layout Schemes to Improve ESD Robustness of I/O Buffers in Fully Silicided CMOS Process

Ming-Dou Ker, Wuu-Trong Shieh, I-Ju Wei, 2009, IEEE Transactions on Electron Devices.

Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process

Chun-Yu Lin, Ming-Dou Ker, Wen-Yi Chen, 2010, 2010 International Symposium on Next Generation Electronics.

On-glass digital-to-analog converter with gamma correction for panel data driver

Ming-Dou Ker, Tzu-Ming Wang, Yu-Hsuan Li, 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

ESD protection design for high-speed applications in CMOS technology

Ming-Dou Ker, Chun-Yu Lin, Jie-Ting Chen, 2016, 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS).

Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process

Ming-Dou Ker, Wen-Yi Chen, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

Area-Efficient and Low-Leakage Diode String for On-Chip ESD Protection

Chun-Yu Lin, Ming-Dou Ker, Po-Han Wu, 2016, IEEE Transactions on Electron Devices.

Protection design against system-level ESD transient disturbance on display panels

Tung-Yang Chen, Ming-Dou Ker, Wan-Yen Lin, 2010, 2010 Asia-Pacific International Symposium on Electromagnetic Compatibility.

Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process

Ming-Dou Ker, Yuan-Wen Hsiao, 2009, Microelectron. Reliab..

Design of Dual-Band ESD Protection for 24-/60-GHz Millimeter-Wave Circuits

Chun-Yu Lin, Li-Wei Chu, Ming-Dou Ker, 2013, IEEE Transactions on Device and Materials Reliability.

ESD protection design for low trigger voltage and high latch-up immunity

Ming-Dou Ker, Jen-Chou Tseng, Chia-Ku Tsai, 2010, 2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process

Ming-Dou Ker, Zhicong Luo, M. Ker, 2016, IEEE Transactions on Biomedical Circuits and Systems.

ESD protection to overcome internal gate oxide damage on digital-analog interface of mixed-mode CMOS IC's

Ming-Dou Ker, Ta-Lee Yu, 1996 .

Novel input ESD protection circuit with substrate-triggering technique in a 0.25-/spl mu/m shallow-trench-isolation CMOS technology

Tung-Yang Chen, Chung-Yu Wu, Ming-Dou Ker, 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection

Ming-Dou Ker, Jia-Rong Yeh, Yeh-Ning Jou, 2015, 2015 European Conference on Circuit Theory and Design (ECCTD).

On-Chip ESD Protection Strategies for RF Circuits in CMOS Technology

Ming-Dou Ker, Yuan-Wen Hsiao, 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.

Whole-chip ESD protection scheme for CMOS mixed-mode IC's in deep-submicron CMOS technology

Chung-Yu Wu, Ming-Dou Ker, Hun-Hsien Chang, 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

ESD protection design for high-speed I/O interface of stub series terminated logic (SSTL) in a 0.25-/spl mu/m salicided CMOS process

Ming-Dou Ker, Che-Hao Chuang, 2004, Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2004 (IEEE Cat. No.04TH8743).

Multiple-cell square-type layout design for output transistors in submicron CMOS technology to save silicon area

Tung-Yang Chen, Chung-Yu Wu, Ming-Dou Ker, 1998 .

The Impact of Drift Implant and Layout Parameters on ESD Robustness for On-Chip ESD Protection Devices in 40-V CMOS Technology

Ming-Dou Ker, Wei-Jen Chang, 2007, IEEE Transactions on Device and Materials Reliability.

Efficient layout style of CMOS output buffer to improve driving capability of low-voltage submicron CMOS IC's

Ming-Dou Ker, Tao Cheng, Hun-Hsien Chang, 1995, Proceedings of 4th International Conference on Solid-State and IC Technology.

New transient detection circuit for system-level ESD protection

Ming-Dou Ker, Cheng-Cheng Yen, Chi-Sheng Liao, 2008, 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

New design concept for on-chip ESD protection circuits with already-on device in nanoscale CMOS technology

Ming-Dou Ker, Kuo-Chun Hsu, 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger

Ming-Dou Ker, Hun-Hsien Chang, 2000 .

Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process

Chun-Yu Lin, Ming-Dou Ker, Tang-Long Chang, 2011, 2011 International Reliability Physics Symposium.

Fully process-compatible layout design on bond pad to improve wire bond reliability in CMOS ICs

Ming-Dou Ker, Jeng-Jie Peng, 2002 .

Complementary-SCR ESD protection circuit with interdigitated finger-type layout for input pads of submicron CMOS IC's

Chung-Yu Wu, Ming-Dou Ker, 1995 .

P-178: Design of on-panel readout circuit for touch panel application

Ming-Dou Ker, Tzu-Ming Wang, Yu Hsuan Li, 2010 .

Latchup-free fully-protected ESD protection circuit for input pad of submicron CMOS ICs

Ming-Dou Ker, Tain-Shun Wu, 1997 .

System-Level ESD Protection Design with On-Chip Transient Detection Circuit

Ming-Dou Ker, Cheng-Cheng Yen, Pi-Chia Shih, 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

ESD protection design for CMOS RF integrated circuits

Ming-Dou Ker, Chyh-Yih Chang, M. Ker, 2002, 2001 Electrical Overstress/Electrostatic Discharge Symposium.

Circuit Design of Electrical Stimulator Realized in 0.18μm CMOS Process for Epileptic Seizure Suppression

Ming-Dou Ker, Tzu-Yi Yang, Chun-Yu Lin, 2015, Brain Stimulation.

ESD protection design to overcome internal damage on interface circuits of a CMOS IC with multiple separated power pins

Ming-Dou Ker, Chyh-Yih Chang, Yi-Shu Chang, 2004 .

Physical Mechanism of TLU under the SystemLevel ESD Test

Ming-Dou Ker, Sheng-Fu Hsu, 2009 .

Active device under bond pad to save I/O layout for high-pin-count SOC

Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang, 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process

Ming-Dou Ker, Wen-Yu Lo, Kuo-Chun Hsu, 2002, Proceedings International Symposium on Quality Electronic Design.

Layout Verification For Submicron CMOS Cell Libraries To Improve ESD/latchup Reliability

Ming-Dou Ker, Jiann-Horng Lin, Sue-Mei Hsiao, 1997, Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications.

ESD-Protection Design With Extra Low-Leakage-Current Diode String for RF Circuits in SiGe BiCMOS Process

Ming-Dou Ker, Yuan-Wen Hsiao, Woei-Lin Wu, 2006, IEEE Transactions on Device and Materials Reliability.

ESD Protection Design for Touch Panel Control IC Against Latchup-Like Failure Induced by System-Level ESD Test

Ming-Dou Ker, Wuu-Trong Shieh, Po-Yen Chiu, 2017, IEEE Transactions on Electron Devices.

ESD protection strategy for sub-quarter-micron CMOS technology: gate-driven design versus substrate-triggered design

Tung-Yang Chen, Ming-Dou Ker, 2001, 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517).

Failure analysis of ESD damage in a high-voltage driver IC and the effective ESD protection solution [CMOS]

Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang, 2002, Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614).

Evaluation on efficient measurement setup for transient-induced latchup with bi-polar trigger [CMOS IC reliability]

Ming-Dou Ker, Sheng-Fu Hsu, 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

Over-Voltage Protection on the CC Pin of USB Type-C Interface against Electrical Overstress Events

Ming-Dou Ker, Chao-Yang Ke, 2020, 2020 IEEE International Reliability Physics Symposium (IRPS).

Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events

Ming-Dou Ker, Yung-Chih Liang, Chih-Ting Yeh, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

Design of Multiple-Charge-Pump System for Implantable Biomedical Applications

Ming-Dou Ker, Shiau-Pin Lin, M. Ker, 2018, 2018 IEEE Biomedical Circuits and Systems Conference (BioCAS).

Transient-to-digital converter to detect electrical fast transient (EFT) disturbance for system protection design

Tung-Yang Chen, Ming-Dou Ker, Wan-Yen Lin, 2011, 2011 IEEE International Conference on IC Design & Technology.

Design of ESD protection for RF CMOS power amplifier with inductor in matching network

Chun-Yu Lin, Li-Wei Chu, Ming-Dou Ker, 2012, 2012 IEEE Asia Pacific Conference on Circuits and Systems.

Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology

Chi-Ming Chen, Ming-Dou Ker, Hsin-Chyh Hsu, 2005, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..

A novel LC-tank ESD protection design for Giga-Hz RF circuits

Ming-Dou Ker, Chien-Ming Lee, Chien-I Chou, 2003, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003.

Compact layout rule extraction for latchup prevention in a 0.25-/spl mu/m shallow-trench-isolation silicided bulk CMOS process

Tung-Yang Chen, Howard Tang, Ming-Dou Ker, 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

Investigation on seal-ring rules for IC product reliability in 0.25-mum CMOS technology

Shih-Hung Chen, Ming-Dou Ker, 2005, Microelectron. Reliab..

Digital‐to‐analog converter with gamma correction on glass substrate for TFT‐panel applications

Ming-Dou Ker, Tzu-Ming Wang, Yu-Hsuan Li, 2009 .

MOS-Bounded Diodes for On-Chip ESD Protection in Deep Submicron CMOS Process

Ming-Dou Ker, Che-Hao Chuang, Kun-Hsien Lin, 2005, IEICE Trans. Electron..

CDM ESD protection design with initial-on concept in nanoscale CMOS process

Chun-Yu Lin, Ming-Dou Ker, 2010, 2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

ESD implantations for on-chip ESD protection with layout consideration in 0.18-/spl mu/m salicided CMOS technology

Ming-Dou Ker, Che-Hao Chuang, Wen-Yu Lo, 2005 .

Low-Capacitance SCR With Waffle Layout Structure for On-Chip ESD Protection in RF ICs

Chun-Yu Lin, Ming-Dou Ker, M. Ker, 2007, IEEE Transactions on Microwave Theory and Techniques.

Low-Power Wordline Voltage Generator for Low-Voltage Flash Memory

Ming-Dou Ker, Ya-Chun Chang, Tzu-Ming Wang, 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

Investigation on Board-Level CDM ESD Issue in IC Products

Ming-Dou Ker, Yuan-Wen Hsiao, 2008, IEEE Transactions on Device and Materials Reliability.

Monopolar Biphasic Stimulator With Discharge Function and Negative Level Shifter for Neuromodulation SoC Integration in Low-Voltage CMOS Process

Ming-Dou Ker, Chia-Chi Hsieh, M. Ker, 2021, IEEE Transactions on Biomedical Circuits and Systems.

Design of a Bone-Guided Cochlear Implant Microsystem With Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its In Vivo Verification

Chia-Hsiang Yang, Ming-Dou Ker, Chung-Chih Hung, 2021, IEEE Journal of Solid-State Circuits.

Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit Against False Trigger During Fast Power-ON Events

Ming-Dou Ker, Han-Sheng Huang, 2021, 2021 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

From Bioelectronics to Nanobioelectronics: The Biomedical Electronics Translational Research Center [Highlights]

Ming-Dou Ker, Chung-Yu Wu, Chung-Yu Wu, 2021, IEEE Nanotechnology Magazine.

ROT-Harris: A Dynamic Approach to Asynchronous Interest Point Detection

Chengdong Wu, Sonya A. Coleman, Ming-Dou Ker, 2021, 2021 17th International Conference on Machine Vision and Applications (MVA).

Stacking-MOS Protection Design for Interface Circuits Against Cross-Domain CDM ESD Stresses

Ming-Dou Ker, Cheng-Yun Hsueh, 2021, IEEE Transactions on Electron Devices.

Closed-Loop Neuromodulation System-on-Chip (SoC) for Detection and Treatment of Epilepsy

Ming-Dou Ker, Cheng-Hsiang Cheng, 2021, Handbook of Biochips.

Design of Power-Rail ESD Clamp With Dynamic Timing-Voltage Detection Against False Trigger During Fast Power-ON Events

Ming-Dou Ker, Jie-Ting Chen, 2018, IEEE Transactions on Electron Devices.

Abnormal ESD failure mechanism in high-pin-count BGA packaged ICs due to stressing nonconnected balls

Ming-Dou Ker, Wen-Yu Lo, 2004 .

ESD protection for output pad with well-coupled field-oxide device in 0.5-/spl mu/m CMOS technology

Ming-Dou Ker, Chau-Neng Wu, 1997 .

ESD protection design for mixed-voltage I/O buffer by using stacked-NMOS triggered SCR device

Ming-Dou Ker, Hsin-Chin Jiang, Chien-Hui Chuang, 2001, 2001 Electrical Overstress/Electrostatic Discharge Symposium.

Resistor-Less Design of Power-Rail ESD Clamp Circuit in Nanoscale CMOS Technology

Ming-Dou Ker, Chih-Ting Yeh, 2012, IEEE Transactions on Electron Devices.

ESD Protection Design by Using Only 1×VDD Low-Voltage Devices for Mixed-Voltage I/O Buffers with 3×VDD Input Tolerance

Ming-Dou Ker, Chang-Tzu Wang, 2006, 2006 IEEE Asian Solid-State Circuits Conference.

Design of low-leakage power-rail ESD clamp circuit with MOM capacitor and STSCR in a 65-nm CMOS process

Ming-Dou Ker, Po-Yen Chiu, 2011, 2011 IEEE International Conference on IC Design & Technology.

Gate-Bias Circuit to Achieve 3·VDD Input Tolerance by Using 1·VDD Devices and Single VDD Supply

Ming-Dou Ker, Shih-Lun Chen, 2005 .

Study and Verification on the Latch-Up Path Between I/O pMOS and N-Type Decoupling Capacitors in 0.18- $\mu$ m CMOS Technology

Ming-Dou Ker, Chun-Cheng Chen, 2019, IEEE Transactions on Device and Materials Reliability.

ESD Protection Design With Diode-Triggered Quad-SCR for Separated Power Domains

Ming-Dou Ker, Jie-Ting Chen, 2019, IEEE Transactions on Device and Materials Reliability.

High-Voltage nLDMOS in Waffle-Layout Style With Body-Injected Technique for ESD Protection

Ming-Dou Ker, Wen-Yi Chen, 2009, IEEE Electron Device Letters.

Design and implementation of capacitive sensor readout circuit on glass substrate for touch panel applications

Ming-Dou Ker, Tzu-Ming Wang, M. Ker, 2011, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test.

High-robust ESD protection structure with embedded SCR in high-voltage CMOS process

Ming-Dou Ker, Tien-Hao Tang, Kuan-Cheng Su, 2008, 2008 IEEE International Reliability Physics Symposium.

Analysis of abnormal ESD failure mechanism in high-pin-count BGA packaged ICs due to stressing non-connected balls

Ming-Dou Ker, Wen-Yu Lo, 2003, Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003.

A CMOS bandgap reference circuit for sub-1-V operation without using extra low-threshold-voltage device

Ming-Dou Ker, Jung-Sheng Chen, Ching-Yun Chu, 2004 .

Design on the low-capacitance bond pad for high-frequency I/O circuits in CMOS technology

Ming-Dou Ker, Hsin-Chin Jiang, Chyh-Yih Chang, 2001 .

ESD protection design with the low-leakage-current diode string for RF circuits in BiCMOS SiGe process

Ming-Dou Ker, Woei-Lin Wu, M. Ker, 2005, 2005 Electrical Overstress/Electrostatic Discharge Symposium.

Double snapback characteristics in high-voltage nMOSFETs and the impact to on-chip ESD protection design

Ming-Dou Ker, Kun-Hsien Lin, 2004 .

Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface

Ming-Dou Ker, Chien-Hui Chang, 2002 .

Lateral SCR devices with low-voltage high-current triggering characteristics for output ESD protection in submicron CMOS technology

Ming-Dou Ker, 1998 .

Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product

Ming-Dou Ker, Jen-Chou Tseng, Chih-Yao Huang, 2002, Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.02TH8614).

On-chip ESD protection design for GHz RF integrated circuits by using polysilicon diodes in sub-quarter-micron CMOS process

Ming-Dou Ker, Chyh-Yih Chang, 2001, 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517).

Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-/spl mu/m silicide CMOS process

Ming-Dou Ker, Wen-Yu Lo, M. Ker, 2000, IEEE Journal of Solid-State Circuits.

Fabrication of a miniature CMOS-based optical biosensor.

Chung-Yu Wu, Ming-Dou Ker, Jung-Sheng Chen, 2007, Biosensors & bioelectronics.

Improving Safe-Operating-Area of a 5-V n-Channel Large Array MOSFET in a 0.15- $\mu$ m BCD Process

Ming-Dou Ker, Karuna Nidhi, Tingyou Lin, 2018, IEEE Transactions on Electron Devices.

ESD protection for CMOS output buffer by using modified LVTSCR devices with high trigger current

Ming-Dou Ker, 1997 .

Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology

Chun-Yu Lin, Ming-Dou Ker, Wen-Tai Wang, 2015, 2015 IEEE Nanotechnology Materials and Devices Conference (NMDC).

A bone-guided cochlear implant CMOS microsystem preserving acoustic hearing

Chia-Hsiang Yang, Chung-Yu Wu, Ming-Dou Ker, 2017, 2017 Symposium on VLSI Circuits.

Design of negative charge pump circuit with polysilicon diodes in a 0.25 /spl mu/m CMOS process

Ming-Dou Ker, Hsin-Chin Jiang, Chyh-Yih Chang, 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.

Active electrostatic discharge (ESD) device for on-chip ESD protection in sub-quarter-micron complementary metal-oxide semiconductor (CMOS) process

Ming-Dou Ker, Tang-Kui Tseng, 2004 .

Investigation on the Validity of Holding Voltage in High-Voltage Devices Measured by Transmission-Line-Pulsing (TLP)

Ming-Dou Ker, Wen-Yi Chen, Yeh-Jen Huang, 2008, IEEE Electron Device Letters.

Design and Implementation of Readout Circuit on Glass Substrate for Touch Panel Applications

Ming-Dou Ker, Tzu-Ming Wang, 2010, Journal of Display Technology.

ESD protection for deep-submicron CMOS technology using gate-couple CMOS-trigger lateral SCR structure

Chung-Yu Wu, Ming-Dou Ker, Hun-Hsien Chang, 1995, Proceedings of International Electron Devices Meeting.

Bi-Directional SCR Device with Dual-Triggered Mechanism for ESD Protection in Extended-Voltage-Swing I/O Application

Ming-Dou Ker, Zhe-Wei Jiang, Shih-Hung Chen, 2009 .

Improving ESD robustness of stacked diodes with embedded SCR for RF applications in 65-nm CMOS

Chun-Yu Lin, Li-Wei Chu, Ming-Dou Ker, 2014, 2014 IEEE International Reliability Physics Symposium.

Novel octagonal device structure for output transistors in deep-submicron low-voltage CMOS technology

Ming-Dou Ker, Tain-Shun Wu, 1996 .

ASIC with Interpolator for Incremental Optical Encoders

Ming-Dou Ker, Ching-Fang Lin, Ching-Fen Kao, 2003 .

CMOS chip as luminescent sensor for biochemical reactions

Chung-Yu Wu, Ming-Dou Ker, Wensyang Hsu, 2003 .

ESD implantation for subquarter-micron CMOS technology to enhance ESD robustness

Ming-Dou Ker, Hsin-Chyh Hsu, Jeng-Jie Peng, 2003 .

Novel diode structures and ESD protection circuits in a 1.8-V 0.15-/spl mu/m partially-depleted SOI salicided CMOS process

Ming-Dou Ker, M. Ker, Howard Tang, 2001, Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548).

Improvement on Turn-on Speed of Substrate-Triggered SCR Device by Using Dummy-Gate Structure for On-Chip ESD Protection

Ming-Dou Ker, Kuo-Chun Hsu, M. Ker, 2003 .

Dynamic Holding Voltage SCR (DHVSCR) Device for ESD Protection with high Latch-up Immunity

Ming-Dou Ker, Zi-Ping Chen, 2003 .

Design of 2 × VDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology

Ming-Dou Ker, Chang-Tzu Wang, 2010 .

New layout scheme to improve ESD robustness of I/O buffers in fully-silicided CMOS process

Ming-Dou Ker, Wuu-Trong Shieh, I-Ju Wei, 2009, 2009 31st EOS/ESD Symposium.

Design of Fin-Diode-Triggered Rotated Silicon-Controlled Rectifier for High- Speed Digital Application in 16-nm FinFET Process

Chun-Yu Lin, Ming-Dou Ker, M. Ker, 2020, IEEE Transactions on Electron Devices.

Evaluation of subcortical grey matter abnormalities in patients with MRI-negative cortical epilepsy determined through structural and tensor magnetic resonance imaging

Chung-Yu Wu, Ming-Dou Ker, Herming Chiueh, 2014, BMC Neurology.

Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process

Ming-Dou Ker, Yeong-Jar Chang, Po-Yen Chiu, 2009, 2009 IEEE International Reliability Physics Symposium.

ESD protection consideration in nanoscale CMOS technology

Chun-Yu Lin, Ming-Dou Ker, 2011, 2011 11th IEEE International Conference on Nanotechnology.

ESD protection to overcome internal gate oxide damage on digital-analog interface of mixed-mode CMOS IC's

Ming-Dou Ker, Ta-Lee Yu, 1996, Proceedings of the 7th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis.

Protection for Mixed-Voltage I / O in Low-Voltage Thin-Oxide CMOS

Ming-Dou Ker, Wen-Yi Chen, Wei-Jen Chang, 2006 .

ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness

Chien-Ming Lee, Ming-Dou Ker, Hong-Sing Kao, 2002, 2002 IEEE MTT-S International Microwave Symposium Digest (Cat. No.02CH37278).

New Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm Low-Voltage CMOS Process

Ming-Dou Ker, Po-Yen Chiu, 2011, IEEE Transactions on Device and Materials Reliability.

Comparison Between High-Holding-Voltage SCR and Stacked Low-Voltage Devices for ESD Protection in High-Voltage Applications

Ming-Dou Ker, Chia-Tsen Dai, 2018, IEEE Transactions on Electron Devices.