M.-C. Shiau

The signal delay in interconnection lines considering the effects of small-geometry CMOS inverters

M.-C. Shiau, Chih-Feng Wu, Chung-Yu Wu, 1990 .

A new interconnection delay model considering the effects of short-channel logic gates

Chung-Yu Wu, M.-C. Shiau, Ming-Chuen Shiau, 1988, 1988., IEEE International Symposium on Circuits and Systems.

Delay models and speed improvement techniques for RC tree interconnections among small-geometry CMOS inverters

M.-C. Shiau, Chung-Shiang Wu, Ming-Chuen Shiau, 1990 .