Akashi Satoh

发表

FPGA implementation of new standard hash function Keccak

Tatsuya Honda, Hendra Guntur, Akashi Satoh, 2014, 2014 IEEE 3rd Global Conference on Consumer Electronics (GCCE).

FPGA implementation of authenticated encryption algorithm Minalpher

Akashi Satoh, Makiko Kosug, Masahiro Yasuda, 2015, 2015 IEEE 4th Global Conference on Consumer Electronics (GCCE).

Biasing power traces to improve correlation in power analysis attacks

Yongdae Kim, Akashi Satoh, Naofumi Homma, 2010 .

Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates

Takeshi Sugawara, Ingrid Verbauwhede, Kazuo Ohta, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Performance of Physical Unclonable Functions with Shift-Register-Based Post-processing

Akashi Satoh, Yohei Hori, Toshihiro Katashita, 2012 .

SPA against an FPGA-Based RSA Implementation with a High-Radix Montgomery Multiplier

Akashi Satoh, Takafumi Aoki, Naofumi Homma, 2007, 2007 IEEE International Symposium on Circuits and Systems.

PUF evaluation with post-processing and modified modeling attack

Akashi Satoh, Yohei Hori, Toshihiro Katashita, 2013 .

Electromagnetic information leakage for side-channel analysis of cryptographic modules

Akashi Satoh, Takafumi Aoki, Naofumi Homma, 2010, 2010 IEEE International Symposium on Electromagnetic Compatibility.

Evaluation of Simple/Comparative Power Analysis against an RSA ASIC implementation

Akashi Satoh, Takafumi Aoki, Naofumi Homma, 2009, 2009 IEEE International Symposium on Circuits and Systems.

ASIC Performance Comparison for the ISO Standard Block Ciphers

Takeshi Sugawara, Akashi Satoh, Takafumi Aoki, 2007 .

Fertilizer Management System for A Compact Hydroponic Planter

Akashi Satoh, Kaori Uehara, Hiromichi Ikeda, 2019, 2019 IEEE 8th Global Conference on Consumer Electronics (GCCE).

A 10 Gbps full-AES crypto design with a twisted-BDD S-Box architecture

Akashi Satoh, Sumio Morioka, 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Secure implementation of cryptographic modules

Akashi Satoh, Hirofumi Sakane, Toshihiro Katashita, 2010 .

Hardware implementations of hash function Luffa

Takeshi Sugawara, Akashi Satoh, Takafumi Aoki, 2010, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

High-accuracy and low-cost sensor module for hydroponic culture system

Akashi Satoh, Tomohiro Nishimura, Yuji Okuyama, 2016, 2016 IEEE 5th Global Conference on Consumer Electronics.

A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation

Makoto Nagata, Akashi Satoh, Yohei Hori, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Mechanism behind Information Leakage in Electromagnetic Analysis of Cryptographic Modules

Takeshi Sugawara, Yu-ichi Hayashi, Takaaki Mizuki, 2009, WISA.

High-Performance Architecture for Concurrent Error Detection for AES Processors

Takeshi Sugawara, Akashi Satoh, Takafumi Aoki, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Compact Rijndael Hardware Architecture with S-Box Optimization

Akashi Satoh, Seiji Munetoh, Kohji Takano, 2001, ASIACRYPT.

Enhanced Correlation Power Analysis Using Key Screening Technique

Takeshi Sugawara, Akashi Satoh, Takafumi Aoki, 2008, 2008 International Conference on Reconfigurable Computing and FPGAs.

Information leakage from cryptographic hardware via common-mode current

Hiroshi Inoue, Yu-ichi Hayashi, Takaaki Mizuki, 2010, 2010 IEEE International Symposium on Electromagnetic Compatibility.

High-Performance Concurrent Error Detection Scheme for AES Hardware

Takeshi Sugawara, Akashi Satoh, Takafumi Aoki, 2008, CHES.

Area reduction and improvements in speed and compression ratio for a Lempel–Ziv data compression circuit using a content addressable memory

Akashi Satoh, A. Satoh, 1999 .

Information leakage from cryptographic hardware via common-mode current

Takeshi Sugawara, Hiroshi Inoue, Yu-ichi Hayashi, 2010, 2010 IEEE International Symposium on Electromagnetic Compatibility.

Side-channel Attack user reference architecture board SAKURA-W for security evaluation of IC card

Akashi Satoh, Masato Matsubayashi, 2015, 2015 IEEE 4th Global Conference on Consumer Electronics (GCCE).

Performance Evaluation for PUF-based Authentication Systems with Shift Post-processing : Additional Experimental Results

Akashi Satoh, Toshihiro Katashita, Hyunho Kang Yohei Hori, 2011 .

On-demand design service innovations

Akashi Satoh, Hiroshi Ishikawa, Toru Aihara, 2004, IBM J. Res. Dev..

Collision-Based Power Analysis of Modular Exponentiation Using Chosen-Message Pairs

Adi Shamir, Akashi Satoh, Takafumi Aoki, 2008, CHES.

DPA Using Phase-Based Waveform Matching against Random-Delay Countermeasure

Akashi Satoh, Takafumi Aoki, Naofumi Homma, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Side-channel AttacK User Reference Architecture board SAKURA-G

Hendra Guntur, Akashi Satoh, Jun Ishii, 2014, 2014 IEEE 3rd Global Conference on Consumer Electronics (GCCE).

GPGPU software implementation of authenticated encryption algorithm Minalpher

Akashi Satoh, Makiko Kosugi, 2016, 2016 IEEE 5th Global Conference on Consumer Electronics.

A Hydroponic Planter System to enable an Urban Agriculture Service Industry

Akashi Satoh, 2018, 2018 IEEE 7th Global Conference on Consumer Electronics (GCCE).

Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers

Akashi Satoh, Takafumi Aoki, Naofumi Homma, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Compact ASIC Architectures for the 512-Bit Hash Function Whirlpool

Takeshi Sugawara, Akashi Satoh, Takafumi Aoki, 2008, WISA.

Is the differential frequency-based attack effective against random delay insertion?

Máire O'Neill, John V. McCanny, Akashi Satoh, 2009, 2009 IEEE Workshop on Signal Processing Systems.

Hardware Architecture and Cost Estimates for Breaking SHA-1

Akashi Satoh, Akashi Satoh, 2005, ISC.

A Configurable On-Chip Glitchy-Clock Generator for Fault Injection Experiments

Takeshi Sugawara, Akashi Satoh, Takafumi Aoki, 2012, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Compact and high-speed hardware architectures for hash function tiger

Akashi Satoh, Nicolas Sklavos, 2009, 2009 IEEE International Symposium on Circuits and Systems.

Comparison of side-channel attack on cryptographic cirucits between old and new technology FPGAs

Akashi Satoh, Kohei Sawada, Masato Matsubayashi, 2016, 2016 IEEE 5th Global Conference on Consumer Electronics.

Chosen-message SPA attacks against FPGA-based RSA hardware implementations

Akashi Satoh, Takafumi Aoki, Naofumi Homma, 2008, 2008 International Conference on Field Programmable Logic and Applications.

Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs

Akashi Satoh, Yohei Hori, Toshihiro Katashita, 2010, 2010 International Conference on Reconfigurable Computing and FPGAs.

Development of an on-chip micro shielded-loop probe to evaluate performance of magnetic film to protect a cryptographic LSI from electromagnetic analysis

Takeshi Sugawara, Akashi Satoh, Takafumi Aoki, 2010, 2010 IEEE International Symposium on Electromagnetic Compatibility.

A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques

Daisuke Suzuki, Minoru Saeki, Akashi Satoh, 2009, CHES.

An on-chip glitchy-clock generator for testing fault injection attacks

Takeshi Sugawara, Akashi Satoh, Takafumi Aoki, 2011, Journal of Cryptographic Engineering.

Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function

Akashi Satoh, Yohei Hori, Toshihiro Katashita, 2011, 2011 International Conference on Reconfigurable Computing and FPGAs.

Systematic design of high-radix Montgomery multipliers for RSA processors

Akashi Satoh, Takafumi Aoki, Naofumi Homma, 2008, 2008 IEEE International Conference on Computer Design.

Development of a high bandwidth merged logic/DRAM multimedia chip

Rajiv V. Joshi, Wei Hwang, Akashi Satoh, 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

A compact hardware design of a sensor module for hydroponics

Akashi Satoh, Tomohiro Nishimura, Yuji Okuyama, 2017, 2017 IEEE 6th Global Conference on Consumer Electronics (GCCE).

Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems

Kenji Toda, Akashi Satoh, Hirofumi Sakane, 2008, 2008 International Conference on Field Programmable Logic and Applications.

High-Performance Hardware Architectures for Galois Counter Mode

Akashi Satoh, Takafumi Aoki, Takeshi Sugawara, 2009, IEEE Transactions on Computers.

High-Speed MARS Hardware

Akashi Satoh, Kohji Takano, Edward D'Avignon, 2000, AES Candidate Conference.

A High-Performance ASIC Implementation of the 64-bit Block Cipher CAST-128

Takeshi Sugawara, Akashi Satoh, Takafumi Aoki, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Prototyping platform for performance evaluation of SHA-3 candidates

Ingrid Verbauwhede, Kazuo Ohta, Akashi Satoh, 2010, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

Clock glitch generator on SAKURA-G for fault injection attack against a cryptographic circuit

Akashi Satoh, Jun Ishii, Masato Matsubayashi, 2016, 2016 IEEE 5th Global Conference on Consumer Electronics.

Enhanced power analysis attack using chosen message against RSA hardware implementations

Akashi Satoh, Takafumi Aoki, Naofumi Homma, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Unified Hardware Architecture for 128-Bit Block Ciphers AES and Camellia

Akashi Satoh, Sumio Morioka, 2003, CHES.

Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption

Kenji Toda, Akashi Satoh, Hirofumi Sakane, 2013, IEICE Trans. Inf. Syst..

Lempel‐Ziv‐type high‐speed data compression circuit using content addressable memory

Akashi Satoh, Hideto Niijima, 1995 .

A High-Speed Small RSA Encryption LSI with Low Power Dissipation

Akashi Satoh, Seiji Munetoh, Y. Kobayashi, 1997, ISW.

Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays

Kazukuni Kobara, Akashi Satoh, Yohei Hori, 2014, J. Inf. Process..

High-Speed Pipelined Hardware Architecture for Galois Counter Mode

Takeshi Sugawara, Akashi Satoh, Takafumi Aoki, 2007, ISC.

ASIC-hardware-focused comparison for hash functions MD5, RIPEMD-160, and SHS

Akashi Satoh, Tadanobu Inoue, 2007, Integr..

Security evaluation of cryptographic modules against side-channel attack using a biased data set

Hendra Guntur, Akashi Satoh, Masato Matsubayashi, 2017, 2017 IEEE 6th Global Conference on Consumer Electronics (GCCE).

High-performance ASIC implementations of the 128-bit block cipher CLEFIA

Takeshi Sugawara, Akashi Satoh, Takafumi Aoki, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Comparative Power Analysis of Modular Exponentiation Algorithms

Adi Shamir, Akashi Satoh, Takafumi Aoki, 2010, IEEE Transactions on Computers.

ASIC hardware implementations for 512-bit hash function Whirlpool

Akashi Satoh, 2008, 2008 IEEE International Symposium on Circuits and Systems.

ASIC hardware focused comparison for hash functions MD5, RIPEMD-160, and SHS

Akashi Satoh, Tadanobu Inoue, T. Inoue, 2005, International Conference on Information Technology: Coding and Computing (ITCC'05) - Volume II.

A High-Resolution Phase-Based Waveform Matching and Its Application to Side-Channel Attacks

Takeshi Sugawara, Akashi Satoh, Takafumi Aoki, 2007 .

Development of side-channel attack standard evaluation environment

Takeshi Sugawara, Akashi Satoh, Takafumi Aoki, 2009, 2009 European Conference on Circuit Theory and Design.

A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture

Akashi Satoh, Sumio Morioka, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI

Akashi Satoh, Sumio Morioka, 2002, ISC.

A fast power current analysis methodology using capacitor charging model for side channel attack evaluation

Makoto Nagata, Akashi Satoh, Yohei Hori, 2011, 2011 IEEE International Symposium on Hardware-Oriented Security and Trust.

Hardware-Focused Performance Comparison for the Standard Block Ciphers AES, Camellia, and Triple-DES

Akashi Satoh, Sumio Morioka, 2003, ISC.

High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching

Akashi Satoh, Takafumi Aoki, Naofumi Homma, 2006, CHES.

A Logic Design Methodology of Low-power AES Cryptographic Circuits

Akashi Satoh, Sumio Morioka, 2003 .

A PostScript printer controller embedded with Lempel–Ziv data compression function

Akashi Satoh, Makoto Ueda, Tsuyoshi Satoh, 1998 .

Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems

Kenji Toda, Akashi Satoh, Hirofumi Sakane, 2008, IWSEC.

High-Speed Parallel Hardware Architecture for Galois Counter Mode

Akashi Satoh, 2007, 2007 IEEE International Symposium on Circuits and Systems.

A Scalable Dual-Field Elliptic Curve Cryptographic Processor

Akashi Satoh, Kohji Takano, 2003, IEEE Trans. Computers.

Profiling attack using multivariate regression analysis

Takeshi Sugawara, Akashi Satoh, Takafumi Aoki, 2010, IEICE Electron. Express.

An Optimized S-Box Circuit Architecture for Low Power AES Design

Akashi Satoh, Sumio Morioka, A. Satoh, 2002, CHES.

A Design Methodology for a DPA-Resistant Circuit with RSL Techniques

Daisuke Suzuki, Minoru Saeki, Tsutomu Matsumoto, 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Differential power analysis of AES ASIC implementations with various S-box circuits

Takeshi Sugawara, Akashi Satoh, Takafumi Aoki, 2009, 2009 European Conference on Circuit Theory and Design.

A First Report on Electromagnetic and Power Analysis Attacks against a 28-nm FPGA Device

Akashi Satoh, Yohei Hori, Toshihiro Katashita, 2013 .

EMC ’ 09 / Kyoto Spectrum Analysis of Cryptographic Modules to Counteract Side-Channel Attacks

Takeshi Sugawara, Yu-ichi Hayashi, Takaaki Mizuki, 2009 .

Electromagnetic Side-channel Attack against 28-nm FPGA Device

Akashi Satoh, Yohei Hori, Toshihiro Katashita, 2012 .

EMC ’ 09 / Kyoto An Analysis of Information Leakage from a Cryptographic Hardware via Common-Mode Current

Takeshi Sugawara, Hiroshi Inoue, Yu-ichi Hayashi, 2009 .

A Scalable Hardware Architecture for Elliptic Curve Cryptography on GF(p)

Akashi Satoh, Nobuyuki Ohba, Kohji Takano, 2002 .

Development of a standard evaluation environment for side channel attacks -

Akashi Satoh, Hirofumi Sakane, Toshihiro Katashita, .

Systematic Design of RSA Processors Based on

Akashi Satoh, Takafumi Aoki, Naofumi Homma, 2011 .