Diederik Verkest

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Multimedia systems in a changing technology landscape

Diederik Verkest, 2009, ESTImedia.

A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs

Diederik Verkest, Francky Catthoor, Javier Resano, 2004, Microprocess. Microsystems.

Spatial locality exploitation for runtime reordering of JPEG2000 wavelet data layouts

Rudy Lauwereins, Diederik Verkest, Thanos Stouraitis, 2009, TODE.

Task concurrency management methodology summary

Rudy Lauwereins, Hugo De Man, Diederik Verkest, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

Application of system semantics to VLSI for the transformational design of a parameterized booth multiplier module — a case study

Diederik Verkest, Johan Vanslembrouck, Raymond T. Boute, 1989 .

Design style case study for computer nodes of a heterogeneous NoC platform

Diederik Verkest, Henk Corporaal, Geert Deconinck, 2004 .

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Vassilis Paliouras, Diederik Verkest, Johan Vounckx, 2005, Lecture Notes in Computer Science.

Optimizing the interconnect of future Systems on Chip in deep submicron technology

Diederik Verkest, Serge Vernalde, Anthony Leroy, 2003 .

A Description Methodology for Parameterized Modules in the Boyer-Moore Logic

Hugo De Man, Diederik Verkest, Luc J. M. Claesen, 1992, TPCD.

Low track height standard-cells enable high-placement density and low-BEOL cost (Conference Presentation)

Diederik Verkest, Peter Debacker, Julien Ryckaert, 2017, Advanced Lithography.

Hardware/software co-design of digital telecommunication systems

Diederik Verkest, Bill Lin, Ivo Bolsens, 1997, Proc. IEEE.

A Proof of the Non-Restoring Division Algorithm and its Implementation on the Cathedral-II ALU

Hugo De Man, Diederik Verkest, Luc J. M. Claesen, 1992, Designing Correct Circuits.

Semi Custom Design: A Case Study on SIMD Shufflers

Diederik Verkest, Francky Catthoor, Praveen Raghavan, 2007, PATMOS.

Infrastructure for design and management of relocatable tasks in a heterogeneous reconfigurable system-on-chip

Rudy Lauwereins, Diederik Verkest, Paul Coene, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Evaluation of a complete NoC platform exploiting Spatial Division Multiplexing

Diederik Verkest, Francky Catthoor, Anthony Leroy, 2006 .

Design style case study for embedded multi media compute nodes

Diederik Verkest, Henk Corporaal, Francky Catthoor, 2004, 25th IEEE International Real-Time Systems Symposium.

EMPIRE: Empirical power/area/timing models for register files

Diederik Verkest, Francky Catthoor, Praveen Raghavan, 2009, Microprocess. Microsystems.

Standard-cell design architecture options below 5nm node: The ultimate scaling of FinFET and Nanosheet

Diederik Verkest, Peter Debacker, Julien Ryckaert, 2019, Advanced Lithography.

Operating system based software generation for systems-on-chip

Hugo De Man, Diederik Verkest, Dirk Desmet, 2000, Proceedings 37th Design Automation Conference.

Vertical GAAFETs for the Ultimate CMOS Scaling

Diederik Verkest, Anabela Veloso, Praveen Raghavan, 2015, IEEE Transactions on Electron Devices.

Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism

Diederik Verkest, David Novo, Francky Catthoor, 2006, PATMOS.

TEASE: A systematic analysis framework for early evaluation of FinFET-based advanced technology nodes

Diederik Verkest, Paul Zuber, Julien Ryckaert, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

CFET standard-cell design down to 3Track height for node 3nm and below

Diederik Verkest, Peter Debacker, Julien Ryckaert, 2019, Advanced Lithography.

Métodos de depuración HW-SW para sistemas on chip reconfigurables

Rudy Lauwereins, Diederik Verkest, Jordi Carrabina, 2004 .

Low cost task migration initiation in a heterogeneous MP-SoC

Diederik Verkest, Prabhat Avasare, Jean-Yves Mignolet, 2005, Design, Automation and Test in Europe.

Buried Power Rails and Back-side Power Grids: Arm® CPU Power Delivery Network Design Beyond 5nm

Diederik Verkest, Shidhartha Das, Brian Cline, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Software-Controlled Scratchpad Mapping Strategies for Wavelet-Based Applications

Rudy Lauwereins, Diederik Verkest, Thanos Stouraitis, 2006, 2006 IEEE Workshop on Signal Processing Systems Design and Implementation.

PathFinding - Determining the technology/design sweetspot

Diederik Verkest, Dragomir Milojevic, Praveen Raghavan, 2008 .

Hierarchical Run-Time Reconfiguration Managed by an Operating System for Reconfigurable Systems

Rudy Lauwereins, Diederik Verkest, Serge Vernalde, 2003, Engineering of Reconfigurable Systems and Algorithms.

Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings

Vassilis Paliouras, Diederik Verkest, Johan Vounckx, 2005, PATMOS.

Design Technology co-optimization for N10

Diederik Verkest, Naoto Horiguchi, Aaron Thean, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

Design technology for networked reconfigurable FPGA platforms

Diederik Verkest, Steven A. Guccione, Ivo Bolsens, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Derivation of formal representations from process-based specification and implementation models

Diederik Verkest, Bill Lin, Gjalt G. de Jong, 1997, Proceedings. Tenth International Symposium on System Synthesis (Cat. No.97TB100114).

Architecture exploration for a reconfigurable architecture template

Rudy Lauwereins, Diederik Verkest, Andy Lambrechts, 2005, IEEE Design & Test of Computers.

NoC based implementation: MPSoC for high-performance, low-power video coding application

Diederik Verkest, Philippe Martin, Dragomir Milojevic, 2009 .

Architectural strategies in standard-cell design for the 7 nm and beyond technology node

Diederik Verkest, Farshad Firouzi, Peter Debacker, 2016 .

Modeling FinFET metal gate stack resistance for 14nm node and beyond

Diederik Verkest, Aaron Thean, Piet Wambacq, 2015, 2015 International Conference on IC Design & Technology (ICICDT).

Enabling word-width aware energy optimizations for embedded processors

Diederik Verkest, Francky Catthoor, Praveen Raghavan, 2007 .

A novel architecture for efficient protocol processing in high speed communication environments

Diederik Verkest, Gregory Doumenis, Theofanis Orphanoudakis, 2000, 1st European Conference on Universal Multiservice Networks. ECUMN'2000 (Cat. No.00EX423).

Special report: machine chameleon

Diederik Verkest, 2003 .

Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs

Diederik Verkest, Paul Marchal, Francky Catthoor, 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

Run-Time Management of a MPSoC Containing FPGA Fabric Tiles

Diederik Verkest, Henk Corporaal, Hendrik Eeckhaut, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications

Diederik Verkest, Francky Catthoor, Miguel Corbalan, 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).

Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM

Diederik Verkest, Piet Wambacq, Julien Ryckaert, 2015, 2015 International Conference on IC Design & Technology (ICICDT).

Run-Time Scheduling for Multimedia Applications on Dynamically Reconfigurable Systems

Diederik Verkest, Francky Catthoor, Javier Resano, 2003, ESTImedia.

Formalized three-layer system-level reuse model and methodology for embedded data-dominated applications

Hugo De Man, Diederik Verkest, Francky Catthoor, 2000, DATE '00.

Power-efficient flexible processor architecture for embedded applications

Hugo De Man, Diederik Verkest, Francky Catthoor, 2003, IEEE Trans. Very Large Scale Integr. Syst..

A Customized Cross-Bar for Data-Shuffling in Domain-Specific SIMD Processors

Diederik Verkest, Francky Catthoor, Praveen Raghavan, 2007, ARCS.

Power exploration for dynamic data types through virtual memory management refinement

Hugo De Man, Diederik Verkest, Francky Catthoor, 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform

Rudy Lauwereins, Hugo De Man, Diederik Verkest, 2000, PACS.

Design system and method for combined design of hardware and software

Diederik Verkest, Bill Lin, Ivo Bolsens, 1996 .

A novel structure of MOSFET array to measure ioff-ion with high accuracy and high density

Diederik Verkest, Eric Beyne, Hidetoshi Ohnuma, 2015, Proceedings of the 2015 International Conference on Microelectronic Test Structures.

System-level interconnect architecture exploration for custom memory organizations

Diederik Verkest, Francky Catthoor, Tycho van Meeuwen, 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).

Dimensioning for power and performance under 10nm: The limits of FinFETs scaling

Diederik Verkest, Aaron Thean, Praveen Raghavan, 2015, 2015 International Conference on IC Design & Technology (ICICDT).

Compiler-Driven Leakage Energy Reduction in Banked Register Files

Diederik Verkest, Giovanni De Micheli, Francky Catthoor, 2006, PATMOS.

thereof heterogeneous multiprocessor system in the form of a Network on Chip, and methods and operating system to control

Diederik Verkest, Paul Coene, Serge Vernalde, 2004 .

Design-Time Data-Access Analysis for Parallel Java Programs with Shared-Memory Communication Model

Rudy Lauwereins, Diederik Verkest, Francky Catthoor, 2004, Euro-Par.

Impact of a SADP flow on the design and process for N10/N7 metal layers

Diederik Verkest, Kurt G. Ronse, Julien Ryckaert, 2015, Advanced Lithography.

Analysis of microbump induced stress effects in 3D stacked IC technologies

Diederik Verkest, Bart Vandevelde, Eric Beyne, 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

Characterization and simulation methodology for time-dependent variability in advanced technologies

Diederik Verkest, Francky Catthoor, Dimitri Linten, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

Networks on Chip as Hardware Components of an OS for Reconfigurable Systems

Rudy Lauwereins, Diederik Verkest, Théodore Marescaux, 2003, FPL.

ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix

Rudy Lauwereins, Hugo De Man, Diederik Verkest, 2003, FPL.

DTCO at N7 and beyond: patterning and electrical compromises and opportunities

Diederik Verkest, Kurt G. Ronse, Julien Ryckaert, 2015, Advanced Lithography.

DRESC: a retargetable compiler for coarse-grained reconfigurable architectures

Rudy Lauwereins, Hugo De Man, Diederik Verkest, 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

C-programmable coarse grain processor with breakthrough power efficiency enables the next generation multi-mode nomadic embedded devices

Rudy Lauwereins, Diederik Verkest, Mladen Berekovic, 2005 .

Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation

Rudy Lauwereins, Diederik Verkest, Théodore Marescaux, 2004, FPL.

A Coarse-Grained Array Accelerator for Software-Defined Radio Baseband Processing

Rudy Lauwereins, Liesbet Van der Perre, Diederik Verkest, 2008, IEEE Micro.

An on-chip communication architecture simulator for low-power SoC

Diederik Verkest, Anthony Leroy, Frédéric Robert, 2004 .

Design methodology for a tightly coupled VLIW/reconfigurable matrix architecture: a case study

Rudy Lauwereins, Diederik Verkest, Serge Vernalde, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

A reconfigurable manager for dynamically reconfigurable hardware

Diederik Verkest, Francky Catthoor, Daniel Mozos, 2005, IEEE Design & Test of Computers.

Design of Cam-E-leon, a Run-Time Reconfigurable Web Camera

Diederik Verkest, Théodore Marescaux, Patrick Schaumont, 2002, Embedded Processor Design Challenges.

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies

Diederik Verkest, Anabela Veloso, Aaron Thean, 2014, 2014 44th European Solid State Device Research Conference (ESSDERC).

Requirements for Static Task Scheduling in Real Time Embedded Systems

Diederik Verkest, Francky Catthoor, Chun Wong, 2001 .

Dynamic scheduling of concurrent tasks with cost performance trade-off

Diederik Verkest, Francky Catthoor, Peng Yang, 2000, CASES '00.

Design issues in heterogeneous 3D/2.5D integration

Diederik Verkest, Eric Beyne, Paul Marchal, 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

Designers' Forum : Design, Automation and Test in Europe Conference and Exhibition : Munich, Germany, March 3-7, 2003

Diederik Verkest, Donatella Sciuto, 2003 .

Energy-Aware Runtime Scheduling for Embedded-Multiprocessor SOCs

Rudy Lauwereins, Diederik Verkest, Paul Marchal, 2001, IEEE Des. Test Comput..

Impact of interconnect multiple-patterning variability on SRAMs

Diederik Verkest, Wim Dehaene, Julien Ryckaert, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

C++ based system design of a 72 Mb/s OFDM transceiver for wireless LAN

Diederik Verkest, Patrick Schaumont, Serge Vernalde, 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

Design and Tool Flow of Multimedia MPSoC Platforms

Diederik Verkest, Erik Brockmeyer, Bjorn De Sutter, 2009, J. Signal Process. Syst..

Networks-on-Chip-Based Implementation: MPSoC for Video Coding Applications

Diederik Verkest, Philippe Martin, Dragomir Milojevic, 2009 .

Low power custom crossbars for SIMD shuffles

Diederik Verkest, Francky Catthoor, Praveen Raghavan, 2006 .

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 15th International Workshop, PATMOS 2005, Leuven, Belgium, ... (Lecture Notes in Computer Science)

Vassilis Paliouras, Diederik Verkest, Johan Vounckx, 2005 .

Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor

Diederik Verkest, Francky Catthoor, Praveen Raghavan, 2008, 21st International Conference on VLSI Design (VLSID 2008).

3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot

Diederik Verkest, Bruno Bougard, Eric Beyne, 2009, Proceedings of the IEEE.

Combining software synthesis and hardware/software interface generation to meet hard real-time constraints

Diederik Verkest, Steven Vercauteren, Jan van der Steen, 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor

Diederik Verkest, Tom Vander Aa, Mladen Berekovic, 2008, PATMOS.

Lateral NWFET optimization for beyond 7nm nodes

Diederik Verkest, Aaron Thean, Praveen Raghavan, 2015, 2015 International Conference on IC Design & Technology (ICICDT).

Proposal for unified system design meta flow in task-level and instruction-level design technology research for multi-media applications

Diederik Verkest, Erik Brockmeyer, Francky Catthoor, 1998, Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210).

The economic impact of EUV lithography on critical process modules

Geert Vandenberghe, Diederik Verkest, Naoto Horiguchi, 2014, Advanced Lithography.

Technology/System Codesign and Benchmarking for Lateral and Vertical GAA Nanowire FETs at 5-nm Technology Node

Diederik Verkest, Francky Catthoor, Peter Debacker, 2015, IEEE Transactions on Electron Devices.

Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs

Diederik Verkest, Peter Debacker, Praveen Raghavan, 2016, ISLPED.

Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs

Rudy Lauwereins, Diederik Verkest, Théodore Marescaux, 2002, FPL.

Sequential 3D standard cell 4T architecture using design crenellation and self-aligned MOL for N2 technology and beyond

Diederik Verkest, Julien Ryckaert, Alessio Spessot, 2020 .

System level design using C++

Diederik Verkest, Joachim Kunkel, Frank Schirrmeister, 2000, DATE '00.

Static task scheduling of real-time embedded systems

Diederik Verkest, Francky Catthoor, Chun Wong, 2000 .

Centralized end-to-end flow control in a best-effort network-on-chip

Diederik Verkest, Henk Corporaal, Prabhat Avasare, 2005, EMSOFT.

Exploiting Hierarchical Configuration to Improve Run-Time MPSoC Task Assignment

Diederik Verkest, Henk Corporaal, Prabhat Avasare, 2006, ERSA.

Global multimedia system design exploration using accurate memory organization feedback

Diederik Verkest, Erik Brockmeyer, Francky Catthoor, 1999, DAC '99.

Scaling CMOS beyond Si FinFET: an analog/RF perspective

Diederik Verkest, A. Vandooren, Geert Hellings, 2018, 2018 48th European Solid-State Device Research Conference (ESSDERC).

Proceedings : Design, Automation and Test in Europe Conference and Exhibition : Munich, Germany, March 3-7, 2003

Norbert Wehn, Diederik Verkest, 2003 .

Designing an operating system for a heterogeneous reconfigurable SoC

Rudy Lauwereins, Diederik Verkest, Paul Coene, 2003, Proceedings International Parallel and Distributed Processing Symposium.

Optimisation problems for dynamic concurrent task-based systems

Diederik Verkest, Paul Marchal, Chun Wong, 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

Formalized three-layer system-level model and reuse methodology for embedded data-dominated applications

Hugo De Man, Diederik Verkest, Francky Catthoor, 2000, IEEE Trans. Very Large Scale Integr. Syst..

Empirical power/area/timing model for register files

Diederik Verkest, Francky Catthoor, Praveen Raghavan, 2005 .

Object-distribution analysis for program decomposition and re-clustering

Diederik Verkest, Francky Catthoor, Richard Stahl, 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

Description and verification of more-dimensional regular and non-homogeneous structures using a functional hardware description language

Diederik Verkest, Luc Claesen, W. Ploegaerts, 1989 .

Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs

Diederik Verkest, Aaron Thean, Piet Wambacq, 2016, SPIE Advanced Lithography.

Flexible hardware acceleration for multimedia oriented microprocessors

Hugo De Man, Diederik Verkest, Francky Catthoor, 2000, MICRO 33.

Exploiting the Expressiveness of Cyclo-Static Dataflow to Model Multimedia Implementations

Diederik Verkest, Henk Corporaal, Kristof Denolf, 2007, EURASIP J. Adv. Signal Process..

Holisitic device exploration for 7nm node

Diederik Verkest, Naoto Horiguchi, Aaron Thean, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

FQ-Conv: Fully Quantized Convolution for Efficient and Accurate Inference pdf

Diederik Verkest, Peter Debacker, Stefan Cosemans, 2019, ArXiv.

Concepts and Implementation of Spatial Division Multiplexing for Guaranteed Throughput in Networks-on-Chip

Diederik Verkest, Francky Catthoor, Dragomir Milojevic, 2008, IEEE Transactions on Computers.

Distributed Loop Controller Architecture for Multi-threading in Uni-threaded VLIW Processors

Diederik Verkest, Francky Catthoor, Praveen Raghavan, 2006, Proceedings of the Design Automation & Test in Europe Conference.

A Safari Through the MPSoC Run-Time Management Jungle

Diederik Verkest, Henk Corporaal, Vincent Nollet, 2010, J. Signal Process. Syst..

Modeling and exploiting spatial locality trade-offs in wavelet-based applications under varying resource requirements

Rudy Lauwereins, Diederik Verkest, Thanos Stouraitis, 2010, TECS.

Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node

Diederik Verkest, Praveen Raghavan, Alessio Spessot, 2017, IEEE Transactions on Electron Devices.

Formal Hardware Verification In Hol And In Boyer-moore: A Comparative Analysis

Hugo De Man, Diederik Verkest, Luc J. M. Claesen, 1991, 1991., International Workshop on the HOL Theorem Proving System and Its Applications.

Task concurrency management experiment for power-efficient speed-up of embedded MPEG4 IM1 player

Rudy Lauwereins, Hugo De Man, Diederik Verkest, 2000, Proceedings 2000. International Workshop on Parallel Processing.

Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling

Rudy Lauwereins, Hugo De Man, Diederik Verkest, 2003, DATE.

Coffee: COmpiler Framework for Energy-Aware Exploration

Diederik Verkest, Francky Catthoor, Praveen Raghavan, 2008, HiPEAC.

Co-Design of DSP Systems

Diederik Verkest, Bill Lin, Ivo Bolsens, 1996 .

Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM

Diederik Verkest, Wim Dehaene, Miguel Corbalan, 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

Object-distribution analysis: technique for parallel loop distribution of object-oriented programs

Diederik Verkest, Francky Catthoor, Richard Stahl, 2005, 2005 International Conference on Parallel Processing Workshops (ICPPW'05).

On the comparison of HOL and Boyer-Moore for formal hardware verification

Hugo De Man, Diederik Verkest, Luc J. M. Claesen, 1993, Formal Methods Syst. Des..

Impact of device and interconnect process variability on clock distribution

Diederik Verkest, Aaron Thean, Praveen Raghavan, 2015, 2015 International Conference on IC Design & Technology (ICICDT).

Spatial locality trade-offs of wavelet-based applications in dynamic execution environments

Diederik Verkest, Gauthier Lafruit, Francky Catthoor, 2008, 2008 IEEE International Conference on Acoustics, Speech and Signal Processing.

Energy aware interconnect exploration of coarse grained reconfigurable processors

Diederik Verkest, Praveen Raghavan, Francky Catthoor, 2005 .

Distributed loop buffer for energy efficiency in VLIW processors

Diederik Verkest, Francky Catthoor, Praveen Raghavan, 2006 .

5nm: Has the time for a device change come?

Diederik Verkest, Peter Debacker, Praveen Raghavan, 2016, 2016 17th International Symposium on Quality Electronic Design (ISQED).

Layout optimization and trade-off between 193i and EUV-based patterning for SRAM cells to improve performance and process variability at 7nm technology node

Diederik Verkest, Aaron Thean, Julien Ryckaert, 2015, Advanced Lithography.

Memory Hierarchy Energy Cost of a Direct Filtering Implementation of the Wavelet Transform

Rudy Lauwereins, Diederik Verkest, Gauthier Lafruit, 2005, PATMOS.

A digital intensive circuit for low-frequency noise monitoring in 28nm CMOS

Diederik Verkest, Aaron Thean, Piet Wambacq, 2015, 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Efficient place and route enablement of 5-tracks standard-cells through EUV compatible N5 ruleset

Diederik Verkest, Mladen Berekovic, Julien Ryckaert, 2018, Advanced Lithography.

Topology adaptive network-on-chip design and implementation

Rudy Lauwereins, Diederik Verkest, Serge Vernalde, 2005 .

IMEC N7, N5 and beyond: DTCO, STCO and EUV insertion strategy to maintain affordable scaling trend

Diederik Verkest, Kurt G. Ronse, Jae Uk Lee, 2018, Advanced Lithography.

CoWare—A design environment for heterogeneous hardware/software systems

Hugo De Man, Diederik Verkest, Ivo Bolsens, 1996, EURO-DAC '96/EURO-VHDL '96.

Timed executable system specification of an ADSL modem using a C++ based design environment: A case study

Hugo De Man, Diederik Verkest, Prabhat Avasare, 1999, Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450).

Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond

Diederik Verkest, Piet Wambacq, Julien Ryckaert, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Real-time high-definition stereo matching on FPGA

Diederik Verkest, Gauthier Lafruit, Ke Zhang, 2011, FPGA '11.

SRAM designs for 5nm node and beyond: Opportunities and challenges

Diederik Verkest, Julien Ryckaert, Trong Huynh Bao, 2017, 2017 IEEE International Conference on IC Design and Technology (ICICDT).

Enabling hardware-software multitasking on a reconfigurable computing platform for networked portable multimedia appliances

Rudy Lauwereins, Diederik Verkest, Serge Vernalde, 2002 .

Distributed Loop Controller for Multithreading in

Diederik Verkest, Francky Catthoor, Praveen Raghavan, 2009 .

Creating Tomorrow's Applications through Deeper Collaboration Between Technology and Design

Diederik Verkest, Jan Provoost, Gilbert Declerck, 2015 .

Application of task concurrency management on dynamically reconfigurable hardware platforms

Diederik Verkest, Francky Catthoor, Javier Resano, 2003, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003..

Cost-aware strength reduction for constant multiplication in VLIW processors

Diederik Verkest, Francky Catthoor, Praveen Raghavan, 2008 .

Correctness proofs of parameterized hardware modules in the Cathedral-II synthesis environment

Hugo De Man, Diederik Verkest, Luc J. M. Claesen, 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications

Diederik Verkest, Dragomir Milojevic, Luc Montperrus, 2009, J. Signal Process. Syst..

Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures

Diederik Verkest, Francky Catthoor, Praveen Raghavan, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Energy-aware exploration of coarse grained reconfigurable processors

Diederik Verkest, Francky Catthoor, Praveen Raghavan, 2005 .

CoWare - a design environment for heterogenous hardware/software systems

Hugo De Man, Diederik Verkest, Ivo Bolsens, 1996, EURO-DAC.

Comparison of interconnection network parameters for reconfigurable systems

Rudy Lauwereins, Diederik Verkest, Francky Catthoor, 2003 .

Impact of fin shape variability on device performance towards 10nm node

Diederik Verkest, Naoto Horiguchi, Geert Hellings, 2015, 2015 International Conference on IC Design & Technology (ICICDT).

Extended design reuse trade-offs in hardware-software architecture mapping

Hugo De Man, Diederik Verkest, Francky Catthoor, 2000, CODES '00.

Power breakdown analysis for a heterogeneous NoC platform running a video application

Diederik Verkest, Henk Corporaal, Francky Catthoor, 2005, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05).

System specification for applications with dynamic data storage and intensive data transfer

Diederik Verkest, Francky Catthoor, Bill Lin, 1999 .

Trades-off between lithography line edge roughness and error-correcting codes requirements for NAND Flash memories

Diederik Verkest, Wim Dehaene, Miguel Corbalan, 2012, Microelectron. Reliab..

Energy aware architecture exploration of a CGRA template

Diederik Verkest, Praveen Raghavan, Andy Lambrechts, 2005 .

Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems

Diederik Verkest, Francky Catthoor, Javier Resano, 2003, FPL.

System-level assessment and area evaluation of Spin Wave logic circuits

Rudy Lauwereins, Diederik Verkest, Luca Gaetano Amarù, 2014, 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java

Rudy Lauwereins, Diederik Verkest, Francky Catthoor, 2003, SCOPES.

Designing single chip systems

Hugo De Man, Diederik Verkest, Bill Lin, 1996 .

Large impact of task-level concurrency transformations on the MPEG4 IM1 player for weakly parallel processor platforms

Rudy Lauwereins, Hugo De Man, Diederik Verkest, 2000 .

Smart-array for pipelined BTI characterization

Diederik Verkest, Dimitri Linten, Guido Groeseneken, 2015, 2015 IEEE International Integrated Reliability Workshop (IIRW).

Guest Editorial

Diederik Verkest, Francky Catthoor, Gaetano Borriello, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Standard cell design in N7: EUV vs. immersion

Diederik Verkest, Mircea Dusa, David Rio, 2015, Advanced Lithography.

Low track height standard cell design in iN7 using scaling boosters

Diederik Verkest, Peter Debacker, Julien Ryckaert, 2017, Advanced Lithography.

DTCO exploration for efficient standard cell power rails

Diederik Verkest, Julien Ryckaert, Bharani Chava, 2018, Advanced Lithography.

Maintaining Moore’s law: enabling cost-friendly dimensional scaling

Diederik Verkest, Kurt G. Ronse, Aaron Thean, 2015, Advanced Lithography.

Adaptive mapping to resource availability for dynamic wavelet-based applications

Rudy Lauwereins, Diederik Verkest, Thanos Stouraitis, 2007, 2007 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia.

Highly scalable network on chip for reconfigurable systems

Rudy Lauwereins, Diederik Verkest, Serge Vernalde, 2003, Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748).

Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications

Rudy Lauwereins, Hugo De Man, Yajun Ha, 2002, FPL.

The need for EUV lithography at advanced technology for sustainable wafer cost

Geert Vandenberghe, Diederik Verkest, Kurt G. Ronse, 2013, Advanced Lithography.

Metal stack optimization for low-power and high-density for N7-N5

Diederik Verkest, Kurt G. Ronse, Mircea Dusa, 2016, SPIE Advanced Lithography.

Run-time support for heterogeneous multitasking on reconfigurable SoCs

Rudy Lauwereins, Diederik Verkest, Théodore Marescaux, 2004, Integr..

STT-MRAM cell design with partial source line planes: improving the trade-off between area and series resistance

Liesbet Van der Perre, Diederik Verkest, Wim Dehaene, 2015, 2015 IEEE Non-Volatile Memory System and Applications Symposium (NVMSA).

Efficient verification using generalized partial order analysis

Diederik Verkest, Bill Lin, Gjalt G. de Jong, 1998, Proceedings Design, Automation and Test in Europe.

Complexity scalable motion-compensated temporal filtering

Diederik Verkest, Peter Schelkens, Adrian Munteanu, 2004, SPIE Optics + Photonics.

CoWare—A Design Environment for Heterogeneous Hardware/Software Systems Received August 24, 1995; Accepted February 14, 1996

Diederik Verkest, Ivo Bolsens, K. Van Rompaey, 2002 .

Operating-system controlled network on chip

Diederik Verkest, Théodore Marescaux, Serge Vernalde, 2004, Proceedings. 41st Design Automation Conference, 2004..

Charge Sharing and Charge Injection A/D Converters for Analog In-Memory Computing

Diederik Verkest, Peter Debacker, Stefan Cosemans, 2021, 2021 19th IEEE International New Circuits and Systems Conference (NEWCAS).

A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration

Diederik Verkest, Peter Debacker, Stefan Cosemans, 2021, 2021 IEEE Custom Integrated Circuits Conference (CICC).

Design-Technology Space Exploration for Energy Efficient AiMC-Based Inference Acceleration

Diederik Verkest, Peter Debacker, Debjyoti Bhattacharjee, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

Noise tolerant ternary weight deep neural networks for analog in-memory inference

Rudy Lauwereins, Diederik Verkest, Wim Dehaene, 2021, 2021 International Joint Conference on Neural Networks (IJCNN).

Impact of Wire Geometry on Interconnect RC and Circuit Delay

Diederik Verkest, Christopher J. Wilson, Aaron Thean, 2016, IEEE Transactions on Electron Devices.

Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)

Norbert Wehn, Diederik Verkest, 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

Static Task Scheduling of Embedded Systems

Diederik Verkest, Francky Catthoor, Curtis Wong, 2000 .

Impact of task-level concurrency transformations on the MPEG 4 IM 1 player for weakly parallel processor platforms

Rudy Lauwereins, Diederik Verkest, Paul Marchal, .