Dionysios I. Reisis

发表

A continuous-flow, Variable-Length FFT SDF architecture

Dionysios I. Reisis, Nikolaos Polychronakis, Emmanouil Tsilis, 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems.

Neuronal connectivity assessment for epileptic seizure prevention: Parallelizing the generalized partial directed coherence on many-core platforms

Dionysios I. Reisis, George Chatzikonstantis, Georgios Georgis, 2014, 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV).

Reduced Complexity Superresolution for Low-Bitrate Video Compression

Dionysios I. Reisis, Georgios Georgis, George Lentaris, 2016, IEEE Transactions on Circuits and Systems for Video Technology.

A VLSI architecture for minimizing the transmission power in OFDM transceivers

Dionysios I. Reisis, Konstantinos Babionitakis, Y. Dagres, 2003, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003.

A real-time motion estimation FPGA architecture

Gregory Doumenis, Dionysios I. Reisis, George Lentaris, 2007, Journal of Real-Time Image Processing.

VLSI Arrays with Reconfigurable Buses

Dionysios I. Reisis, Viktor K. Prasanna, V. Prasanna, 1988, ICS.

Evaluating the performance of a configurable, extensible VLIW processor in FFT execution

David Stevens, Dionysios I. Reisis, Vassilios A. Chouliaras, 2009, 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009).

Design and Comparison of FFT VLSI Architectures for SoC Telecom Applications with Different Flexibility, Speed and Complexity Trade-Offs

Luca Fanucci, Dionysios I. Reisis, Sergio Saponara, 2012, Circuits Syst. Signal Process..

Parallel Robust Absolute Orientation on FPGA for Vision and Robotics

Manolis I. A. Lourakis, Dionysios I. Reisis, Dimitrios Soudris, 2018, 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

A scalable optically-switched datacenter network with multicasting

Dionysios I. Reisis, Paraskevas Bakopoulos, Hercules Avramopoulos, 2016, 2016 European Conference on Networks and Communications (EuCNC).

Single-image super-resolution using low complexity adaptive iterative back-projection

Dionysios I. Reisis, Georgios Georgis, George Lentaris, 2013, 2013 18th International Conference on Digital Signal Processing (DSP).

Addressing technique for parallel memory accessing in radix-2 FFT processors

Dionysios I. Reisis, Nikolaos Vlassopoulos, Konstantinos Nakos, 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

An Efficient Network Analyser Based on Linear Array Architecture

Dionysios I. Reisis, George I. Stassinopoulos, S. N. Metallinos, 1994, Parallel Algorithms Appl..

Parallel Image Processing On Enhanced Arrays

Dionysios I. Reisis, Viktor K. Prasanna, 1987, ICPP.

An efficient multiple precision floating-point multiplier

Dionysios I. Reisis, Vassilios A. Chouliaras, Konstantinos Manolopoulos, 2011, 2011 18th IEEE International Conference on Electronics, Circuits, and Systems.

Verification of a complex SoC; the PRO/sup 3/ case-study

Stylianos Perissakis, Gregory Doumenis, Fotis Karoubalis, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Efficient Systolic Array Mapping of FIR Filters Used in PAM-QAM Modulators

Dionysios I. Reisis, A. Chorevas, D. Reisis, 2003, J. VLSI Signal Process..

An efficient multiple precision floating-point Multiply-Add Fused unit

Dionysios I. Reisis, Vassilios A. Chouliaras, Konstantinos Manolopoulos, 2016, Microelectron. J..

Scheduler Accelerator for TDMA Data Centers

Dionysios I. Reisis, Emmanouel A. Varvarigos, Konstantinos Christodoulopoulos, 2018, 2018 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP).

Study of interpolation filters for motion estimation with application in H.264/AVC encoders

Dionysios I. Reisis, Georgios Georgis, George Lentaris, 2011, 2011 18th IEEE International Conference on Electronics, Circuits, and Systems.

An efficient dual-mode floating-point Multiply-Add Fused Unit

Dionysios I. Reisis, Vassilios A. Chouliaras, Konstantinos Manolopoulos, 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems.

Agora: Agent and market-based resource management for many-core systems

Dionysios I. Reisis, Iraklis Anagnostopoulos, Dimitrios Soudris, 2016, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Efficient field processing cores in an innovative protocol processor system-on-chip

Stylianos Perissakis, Nikos A. Nikolaou, Dionysios I. Reisis, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

An Efficient H.264 VLSI Advanced Video Encoder

Gregory Doumenis, Dionysios I. Reisis, George Lentaris, 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

Design and Implementation of a Low-Cost Highly-Modular ATM Access Node Switch

Kostas Pramataris, Dionysios I. Reisis, George I. Stassinopoulos, 1999, Applied Informatics.

Conflict free, parallel memory access for radix-2 FFT processors

Dionysios I. Reisis, Nikolaos Polychronakis, Emmanouil Tsilis, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

A Parallel VLSI Video/Communication Controller

Gregory Doumenis, Dionysios I. Reisis, George E. Konstantoulakis, 2001, J. VLSI Signal Process..

Image computations on reconfigurable VLSI arrays

Dionysios I. Reisis, Viktor K. Prasanna, Russ Miller, 1988, Proceedings CVPR '88: The Computer Society Conference on Computer Vision and Pattern Recognition.

Parity Based In-Place FFT Architecture for Continuous Flow Applications

Dionysios I. Reisis, Dimitrios Soudris, George Lentaris, 2018, 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Parallel Computations on Reconfigurable Meshes

Dionysios I. Reisis, Viktor K. Prasanna, Russ Miller, 1993, IEEE Trans. Computers.

A Graphics Parallel Memory Organization Exploiting Request Correlations

Dionysios I. Reisis, George Lentaris, D. Reisis, 2010, IEEE Transactions on Computers.

Image Computations on Meshes with Multiple Broadcast

Dionysios I. Reisis, Viktor K. Prasanna, V. Prasanna, 1989, IEEE Trans. Pattern Anal. Mach. Intell..

Signal processing for deep-sea observatories with reconfigurable hardware

Dionysios I. Reisis, Georgios Georgis, A. Belias, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

Using high-level synthesis to build memory and datapath optimized DSP accelerators

Dionysios I. Reisis, Dionysios Diamantopoulos, George Economakos, 2014, 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Switching functions of a data center Top-of-Rack (ToR)

Dionysios I. Reisis, Ioannis Patronas, Angelos Kyriakos, 2016, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS).

PANDA: asymmetric passive optical network for xDSL and FTTH access

Dionysios I. Reisis, Ioannis Tomkos, Dimitrios Klonidis, 2013, PCI '13.

An efficient convex hull computation on the reconfigurable mesh

Dionysios I. Reisis, 1992, Proceedings Sixth International Parallel Processing Symposium.

Exact Max-Log MAP Soft-Output Sphere Decoding via Approximate Schnorr–Euchner Enumeration

Dionysios I. Reisis, Konstantinos Nikitopoulos, Athanasios Karachalios, 2015, IEEE Transactions on Vehicular Technology.

Conflict-Free Parallel Memory Accessing Techniques for FFT Architectures

Dionysios I. Reisis, Nikolaos Vlassopoulos, D. Reisis, 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

Parallel Memory Accessing for FFT Architectures

Dionysios I. Reisis, Nikolaos Vlassopoulos, Konstantinos Nakos, 2018, J. Signal Process. Syst..

Data Movement Operations and Applications on Reconfigurable VLSI Arrays

Dionysios I. Reisis, Viktor K. Prasanna, Russ Miller, 1988, ICPP.

A configurable length, Fused Multiply-Add floating point unit for a VLIW processor

Dionysios I. Reisis, Vassilios A. Chouliaras, Konstantinos Manolopoulos, 2009, 2009 IEEE International SOC Conference (SOCC).

A configurable transmitter architecture & organization for XG-PON OLT/ONU/ONT network elements

Dionysios I. Reisis, Georgios Georgis, Nikolaos Liakopoulos, 2015, 2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS).

A High Performance VLSI FFT Architecture

Dionysios I. Reisis, Vassilios A. Chouliaras, Nikolaos Vlassopoulos, 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

Improved graph computations on the reconfigurable mesh

Dionysios I. Reisis, D. Reisis, 1991, [1991] Proceedings. The Fifth International Parallel Processing Symposium.

A real-time H.264/AVC VLSI encoder architecture

Gregory Doumenis, Dionysios I. Reisis, George Lentaris, 2007, Journal of Real-Time Image Processing.

Address Generation Techniques for Conflict Free Parallel Memory Accessing in FFT Architectures

Dionysios I. Reisis, Nikolaos Vlassopoulos, 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

A Co-Design Approach For Rapid Prototyping Of Image Processing On SoC FPGAs

Dionysios I. Reisis, Dimitrios Soudris, Konstantinos Maragos, 2016, PCI.

Customizing a VLIW Chip Multiprocessor for Motion Estimation Algorithms

David Stevens, Dionysios I. Reisis, Vassilios A. Chouliaras, 2011, ARCS Workshops.

NEPHELE: An End-to-End Scalable and Dynamically Reconfigurable Optical Architecture for Application-Aware SDN Cloud Data Centers

Dionysios I. Reisis, Kai Wang, Emmanouel A. Varvarigos, 2018, IEEE Communications Magazine.

Configurable baseband digital transceiver for Gbps wireless 60 GHz communications

Dionysios I. Reisis, Dimitrios Soudris, George Lentaris, 2011, 2011 18th IEEE International Conference on Electronics, Circuits, and Systems.

Customization of an embedded RISC CPU with SIMD extensions for video encoding: A case study

Dionysios I. Reisis, José L. Núñez-Yáñez, Vassilios A. Chouliaras, 2008, Integr..

Programmable Motion Estimation architecture

Dionysios I. Reisis, George Lentaris, Anargyros Drolapas, 2009, 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009).

XG-PON optical network unit downstream FEC design based on truncated Reed-Solomon code

Dionysios I. Reisis, Georgios Georgis, George Synnefakis, 2014, 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS).

A Control-Theoretic Approach for Efficient Design of Filters in DAC and Digital Audio Amplifiers

Dionysios I. Reisis, George Lentaris, Konstantinos S. Tsakalis, 2011, Circuits Syst. Signal Process..

Efficient cascaded VLSI FFT architecture for OFDM systems

Dionysios I. Reisis, Vassilios A. Chouliaras, Nikolaos Vlassopoulos, 2009, 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009).

Design of a Real-Time DSP Engine on RF-SoC FPGA for 5G Networks

Dionysios I. Reisis, Dimitrios Soudris, Giannis Giannoulis, 2019, ONDM.

High Performance 16K, 64K, 256K complex points VLSI Systolic FFT Architectures

Dionysios I. Reisis, Vassilios A. Chouliaras, Nikolaos Vlassopoulos, 2007, 2007 14th IEEE International Conference on Electronics, Circuits and Systems.

Fully Systolic FFT Architecture for Giga-sample Applications

Dionysios I. Reisis, Vassilios A. Chouliaras, Nikolaos Vlassopoulos, 2010, J. Signal Process. Syst..

Demonstration of FPGA-based A-IFoF/mmWave transceiver integration in mobile infrastructure for beyond 5G transport

Dionysios I. Reisis, Dimitrios Soudris, Ioanna Mesogiti, 2021, 2021 European Conference on Optical Communication (ECOC).

FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks

Dionysios I. Reisis, David Steenari, Dimitrios Soudris, 2021, 2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS).