Kiyoung Choi

发表

Hybrid spiking-stochastic Deep Neural Network

Kiyoung Choi, Heesu Kim, Joonsang Yu, 2017, 2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Simulated annealing-based diffusive load balancing on many-core SoC

Kiyoung Choi, Hyunjik Song, 2011, ICAC '11.

Entry control in network-on-chip for memory power reduction

Kiyoung Choi, Sungjoo Yoo, Dongwook Lee, 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

Evaluating memory architectures for media applications on coarse-grained reconfigurable architectures

Kiyoung Choi, Nikil Dutt, Jongeun Lee, 2003, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003.

Efficient instruction encoding for automatic instruction set design of configurable ASIPs

Kiyoung Choi, Nikil Dutt, Jong-eun Lee, 2002, ICCAD 2002.

Memory Operation Inclusive Instruction-Set Extensions and Data Path Generation

Kiyoung Choi, Dongwook Lee, Imyong Lee, 2007, 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP).

Introduction to the Special Issue on the 11th International Conference on Field-Programmable Technology (FPT'12)

Kiyoung Choi, Jason Helge Anderson, 2014, TRETS.

Efficient FPGA acceleration of Convolutional Neural Networks using logical-3D compute array

Kiyoung Choi, Jongeun Lee, Atul Rahman, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable Architectures

Kiyoung Choi, Nikil D. Dutt, Jongeun Lee, 2003, ASAP.

Acceleration of control flow on CGRA using advanced predicated execution

Kiyoung Choi, Kyuseung Han, Jong Kyung Paek, 2010, 2010 International Conference on Field-Programmable Technology.

Synchronization Overhead Reduction in Timed Cosimulation

Kiyoung Choi, Sungjoo Yoo, S. Yoo, 1997 .

Application-specific configuration of multithreaded processor architecture for embedded applications

Kiyoung Choi, Mary Kiemb, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level Prefetching

Kiyoung Choi, Sungjoo Yoo, Junwhan Ahn, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fast Generation of Multiple Custom Instructions under Area Constraints

Kiyoung Choi, Di Wu, Junwhan Ahn, 2011 .

Resonant properties of piezoelectric cantilever transducers fabricated on the SiC membrane

Kiyoung Choi, Jae Hong Park, Dong-Yeon Lee, 2011, 2011 6th IEEE International Conference on Nano/Micro Engineered and Molecular Systems.

Generalized Parameter Extraction Model for High-Speed Interconnects with Arbitrary Boundary Conditions

Kiyoung Choi, Rohit Sharma, Tapas Chakravarty, 2011 .

A Generic Design for Encoding and Decoding Variable Length Codes in Multi-codec Video Processing Engines

Kiyoung Choi, HyoukJoong Lee, V. K. Prasad Arava, 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

Fast custom instruction generation under area constraint

Kiyoung Choi, Di Wu, Imyong Lee, 2010, 2010 International SoC Design Conference.

Performance improvement of geographically distributed cosimulation by hierarchically grouped messages

Kiyoung Choi, Dong Sam Ha, Sungjoo Yoo, 2000, IEEE Trans. Very Large Scale Integr. Syst..

Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture

Kiyoung Choi, Rabi N. Mahapatra, Yoonjin Kim, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Schedulability-driven performance analysis of multiple mode embedded real-time systems

Kiyoung Choi, Youngsoo Shin, Daehong Kim, 2000, DAC.

MPSoC Design Space Exploration Based on Static Analysis of Process Network Model

Kiyoung Choi, Yongjin Ahn, 2007 .

Delay Monitoring System With Multiple Generic Monitors for Wide Voltage Range Operation

Kiyoung Choi, Yonghwan Kim, Wook Kim, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Enhancing schedulability of hard real-time systems through codesign

Kiyoung Choi, Youngsoo Shin, 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

Exploration of trade-offs in the design of volatile STT-RAM cache

Kiyoung Choi, Namhyung Kim, 2016, J. Syst. Archit..

Behavior-to-placed RTL synthesis with performance-driven placement

Kiyoung Choi, Jinhwan Jeon, Daehong Kim, 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs

Kiyoung Choi, Sungjoo Yoo, Byungil Jeong, 2000, ASP-DAC '00.

State-based full predication for low power coarse-grained reconfigurable architecture

Kiyoung Choi, Kyuseung Han, Seongsik Park, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs

Kiyoung Choi, Sungjoo Yoo, Byungil Jeong, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

Binary acceleration using coarse-grained reconfigurable architecture

Kiyoung Choi, Jongeun Lee, Jong Kyung Paek, 2010, CARN.

A new stochastic mutiplier for deep neural networks

Kiyoung Choi, Joonsang Yu, Subin Huh, 2017, 2017 International SoC Design Conference (ISOCC).

Performance improvement of multi-processor systems cosimulation based on SW analysis

Kiyoung Choi, Sungjoo Yoo, Jinyong Jung, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

Low power pipelining of linear systems: a common operand centric approach

Kiyoung Choi, Dongwan Shin, Daehong Kim, 2001, ISLPED '01.

FloRA: Coarse-grained reconfigurable architecture with floating-point operation capability

Kiyoung Choi, Dongwook Lee, Kyuseung Han, 2009, 2009 International Conference on Field-Programmable Technology.

Hybrid Simulation for IP-Based Design

Kiyoung Choi, Young-ran Ma, 1999 .

Dynamic power management of off-chip links for Hybrid Memory Cubes

Kiyoung Choi, Sungjoo Yoo, Junwhan Ahn, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

Speaker Verification based on Deep Neural Network for Text-Constrained Short Commands

Kiyoung Choi, Heesu Kim, Euntae Choi, 2018, 2018 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ASC).

Resource-shared custom instruction generation under performance/area constraints

Di Wu, Kiyoung Choi, Junwhan Ahn, 2012, 2012 International Symposium on System on Chip (SoC).

Optimistic distributed timed cosimulation based on thread simulation model

Kiyoung Choi, Sungjoo Yoo, S. Yoo, 1998, Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98).

Enhancing Utilization of Integer Functional Units for High-Throughput Floating Point Operations on Coarse-Grained Reconfigurable Architecture

Kiyoung Choi, Kyuseung Han, Manhwee Jo, 2013, MUE.

A design framework for hierarchical ensemble of multiple feature extractors and multiple classifiers

Kiyoung Choi, Jin Young Choi, Kyounghoon Kim, 2016, Pattern Recognit..

Loop pipelining in hardware-software partitioning

Kiyoung Choi, Jinhwan Jeon, 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.

Optimal mapping of program overlays onto many-core platforms with limited memory capacity

Kiyoung Choi, M. Balakrishnan, Mansureh Shahraki Moghaddam, 2017, Des. Autom. Embed. Syst..

VHDL Developer's Toolkit 2.6 User's Guide & Reference

Kiyoung Choi, Sanghun Park, 1997 .

Lower-bits cache for low power STT-RAM caches

Kiyoung Choi, Junwhan Ahn, 2012, 2012 IEEE International Symposium on Circuits and Systems.

An adaptive routing algorithm for 3D mesh NoC with limited vertical bandwidth

Kiyoung Choi, Jinho Lee, Mingyang Zhu, 2012, 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC).

Optimizing geographically distributed timed cosimulation by hierarchically grouped messages

Kiyoung Choi, Sungjoo Yoo, 1999, CODES '99.

Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007

Soonhoi Ha, Kiyoung Choi, Nikil Dutt, 2007, CODES+ISSS.

Energy-efficient instruction set synthesis for application-specific processors

Kiyoung Choi, Nikil D. Dutt, Jongeun Lee, 2003, ISLPED '03.

Techniques for improving coarse-grained reconfigurable architectures

Kiyoung Choi, Jongeun Lee, Kyuseung Han, 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

Thor user''s manual: tutorial and commands

Kiyoung Choi, Robert Alverson, Tom Blank, 1988 .

Excavating the Hidden Parallelism Inside DRAM Architectures With Buffered Compares

Kiyoung Choi, Jung Ho Ahn, Jinho Lee, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

CPU-based speed acceleration techniques for shear warp volume rendering

Kiyoung Choi, Changsung Jeong, Sungup Jo, 2012, Multimedia Tools and Applications.

Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture

Kiyoung Choi, Rabi N. Mahapatra, Yoonjin Kim, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Proceedings of the 4th international conference on Hardware/software codesign and system synthesis

Kiyoung Choi, Reinaldo A. Bergamaschi, 2006 .

Adaptive delay monitoring for wide voltage-range operation

Kiyoung Choi, Yonghwan Kim, Wook Kim, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

An Efficient and Accurate Stochastic Number Generator Using Even-Distribution Coding

Kiyoung Choi, Jongeun Lee, Kyounghoon Kim, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Position-based weighted round-robin arbitration for equality of service in many-core network-on-chips

Kiyoung Choi, Hanmin Park, Kiyoung Choi, 2012, NoCArc '12.

Code decomposition and recomposition for enhancing embedded software performance

Kiyoung Choi, Youngchul Cho, Kiyoung Choi, 2009, 2009 Asia and South Pacific Design Automation Conference.

Enforcing Schedulability of Multi-Task Systems by Hardware-Software Codesign

Kiyoung Choi, Youngsoo Shin, 1997, CODES.

Tree-Mesh Heterogeneous Topology for Low-Latency NoC

Kiyoung Choi, Jinho Lee, Sungju Han, 2014, NoCArc '14.

SoC Architecture for Automobile Vision System

Kiyoung Choi, Kyoung Hoon Kim, 2014 .

Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design

Nacer-Eddine Zergainoh, Kiyoung Choi, Sungjoo Yoo, 2003, DATE.

Power conscious fixed priority scheduling for hard real-time systems

Kiyoung Choi, Youngsoo Shin, Youngsoo Shin, 1999, DAC '99.

Mapping control intensive kernels onto coarse-grained reconfigurable array architecture

Kiyoung Choi, Kyungwook Chang, Kiyoung Choi, 2008, 2008 International SoC Design Conference.

A polynomial-time custom instruction identification algorithm based on dynamic programming

Kiyoung Choi, Junwhan Ahn, Imyong Lee, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Efficient Design Space Exploration for Domain-Specific Optimization of Coarse-Grained Reconfigurable Architecture

Kiyoung Choi, Yoonjin Kim, Mary Kiemb, 2005 .

Buffer Size Reduction through Control-Flow Decomposition

Nacer-Eddine Zergainoh, Ahmed Amine Jerraya, Kiyoung Choi, 2007, 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007).

Software synthesis through task decomposition by dependency analysis

Kiyoung Choi, Youngsoo Shin, 1996, ICCAD 1996.

VLSI-SoC: Design for Reliability, Security, and Low Power

Chi-Ying Tsui, Kiyoung Choi, Jae-Joon Kim, 2015, IFIP Advances in Information and Communication Technology.

Deep neural networks with weighted spikes

Kiyoung Choi, Heesu Kim, Jinho Lee, 2018, Neurocomputing.

Backward-annotation of post-layout delay information into high-level synthesis process for performance optimization

Ki-Hyun Kim, Kiyoung Choi, Hyunseok Chang, 1999, ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).

A space- and energy-efficient code compression/decompression technique for coarse-grained reconfigurable architectures

Soonhoi Ha, Kiyoung Choi, Bernhard Egger, 2017, 2017 IEEE/ACM International Symposium on Code Generation and Optimization (CGO).

Multiprocessor system-on-chip designs with active memory processors for higher memory efficiency

Kiyoung Choi, Sungjoo Yoo, Jun-hee Yoo, 2009, 2009 46th ACM/IEEE Design Automation Conference.

Aging Gracefully with Approximation

Kiyoung Choi, Andreas Gerstlauer, Heesu Kim, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

VHDL simulation acceleration using specialized functions

Kiyoung Choi, Taekyoon Ahn, 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

Reconfigurable Architectures

Kiyoung Choi, Mansureh Shahraki Moghaddam, Jae-Min Cho, 2017, Handbook of Hardware/Software Codesign.

Coarse-Grained Reconfigurable Array: Architecture and Application Mapping

Kiyoung Choi, 2011, IPSJ Trans. Syst. LSI Des. Methodol..

Cell division: weight bit-width reduction technique for convolutional neural network hardware accelerators

Kiyoung Choi, Hanmin Park, 2019, ASP-DAC.

Temporal Mapping for Loop Pipelining on a MIMD-style Coarse-Grained Reconfigurable Architecture

Yunheung Paek, Kiyoung Choi, Jonghee Yoon, 2006 .

Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable Architectures

Kiyoung Choi, Nikil D. Dutt, Ganghee Lee, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An Efficient Computer-Aided Prototyping System Based on FPGAs

Kiyoung Choi, Yong-Joo Kim, Kyuseok Kim, 1994 .

Narrow bus encoding for low power systems

Kiyoung Choi, Youngsoo Shin, 2000, ASP-DAC.

Optimizing Timed Cosimulation by Hybrid Synchronization

Kiyoung Choi, Sungjoo Yoo, S. Yoo, 2000, Des. Autom. Embed. Syst..

ESL Design Methodology

Kiyoung Choi, Deming Chen, Philippe Coussy, 2012, J. Electr. Comput. Eng..

Accelerator for Parallel Graph Processing

Kiyoung Choi, Sungpack Hong, Sungjoo Yoo, 2015 .

Fast functional simulation: an incremental approach

Kiyoung Choi, Sun Young Hwang, Tom Blank, 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Power-Conscious Configuration Cache Structure and Code Mapping for Coarse-Grained Reconfigurable Architecture

Yunheung Paek, Kiyoung Choi, Yoonjin Kim, 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

Comparison of Two 3D-stacked Inductive Coupling Communication Interfaces

Kiyoung Choi, Jinho Lee, Mingyang Zhu, 2011 .

An approach to code compression for CGRA

Kiyoung Choi, Seongsik Park, 2011, 2011 3rd Asia Symposium on Quality Electronic Design (ASQED).

Thermal-aware fault-tolerant system design with coarse-grained reconfigurable array architecture

Kiyoung Choi, Ganghee Lee, Kiyoung Choi, 2010, 2010 NASA/ESA Conference on Adaptive Hardware and Systems.

Memory-aware mapping and scheduling of tasks and communications on many-core SoC

Kiyoung Choi, Jinho Lee, 2012, 17th Asia and South Pacific Design Automation Conference.

Chip implementation of a coarse-grained reconfigurable architecture supporting floating-point operations

Kiyoung Choi, Dongwook Lee, Manhwee Jo, 2008, 2008 International SoC Design Conference.

A self-timed divider using RSD number system

Kiyoung Choi, Jun-Woo Kang, KiJong Lee, 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Scheduler implementation in MP SoC design

Nacer-Eddine Zergainoh, Ahmed Amine Jerraya, Kiyoung Choi, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture

Kiyoung Choi, Sungjoo Yoo, Junwhan Ahn, 2016, IEEE Transactions on Computers.

Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model

Kiyoung Choi, Sungjoo Yoo, Sunghyun Lee, 2002, CODES '02.

A mobility analysis method of closed-chain mechanisms with over-constraints and non-holonomic constraints

Kiyoung Choi, Byung-Ju Yi, Whee Kuk Kim, 2004, IEEE International Conference on Robotics and Automation, 2004. Proceedings. ICRA '04. 2004.

Deflection routing in 3D Network-on-Chip with TSV serialization

Kiyoung Choi, Jinho Lee, Dongwook Lee, 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures

Yunheung Paek, Kiyoung Choi, Jonghee W. Yoon, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Adaptively weighted round-robin arbitration for equality of service in a many-core network-on-chip

Kiyoung Choi, Hanmin Park, 2016, IET Comput. Digit. Tech..

Exploiting early partial reconfiguration of run-time reconfigurable FPGAs in embedded systems design (abstract only)

Kiyoung Choi, Sungjoo Yoo, Byungil Jeong, 1999, Symposium on Field Programmable Gate Arrays.

Synthesis of multi-variate stochastic computing circuits

Kiyoung Choi, Kyounghoon Kim, 2017, 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

A design guideline for volatile STT-RAM with ECC and scrubbing

Kiyoung Choi, Namhyung Kim, 2015, 2015 International SoC Design Conference (ISOCC).

An algorithm for mapping loops onto coarse-grained reconfigurable architectures

Kiyoung Choi, Nikil Dutt, Jongeun Lee, 2003 .

FPGA implementation of convolutional neural network based on stochastic computing

Kiyoung Choi, Jongeun Lee, Hossein Moradian, 2017, 2017 International Conference on Field Programmable Technology (ICFPT).

Narrow bus encoding for low-power DSP systems

Kiyoung Choi, Youngsoo Shin, Young-Hoon Chang, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Dynamic operand interchange for low power

Kiyoung Choi, Taekyoon Ahn, Kiyoung Choi, 1997 .

Automatic mapping of application to coarse-grained reconfigurable architecture based on high-level synthesis techniques

Kiyoung Choi, Ganghee Lee, Seokhyun Lee, 2008, 2008 International SoC Design Conference.

High-level synthesis with distributed controller for fast timing closure

Kiyoung Choi, Seokhyun Lee, Kiyoung Choi, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Self-timed divider based on RSD number system

Kiyoung Choi, KiJong Lee, 1996, IEEE Trans. Very Large Scale Integr. Syst..

An integrated hardware-software cosimulation environment for heterogeneous systems prototyping

Soonhoi Ha, Kiyoung Choi, Wonyong Sung, 1995, ASP-DAC '95.

An Investigation to Outlook the Effect of FTA on Motor Car Export to Latin America and the Appropriate Action Plan

Kiyoung Choi, 2012 .

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006

Kiyoung Choi, Reinaldo A. Bergamaschi, Kiyoung Choi, 2006, CODES+ISSS.

Message from the general chairs

Kiyoung Choi, Naehyuck Chang, 2015, VLSI-SoC.

Design space exploration of FPGA accelerators for convolutional neural networks

Kiyoung Choi, Jongeun Lee, Atul Rahman, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Modeling functional unit delays for bit-level chaining

Kiyoung Choi, Seokhyun Lee, Dong-yeob Shin, 2008, 2008 International SoC Design Conference.

Compilation Approach for Coarse-Grained Reconfigurable

Kiyoung Choi, Nikil Dutt, Jongeun Lee, 2003 .

Selectively protecting error-correcting code for area-efficient and reliable STT-RAM caches

Kiyoung Choi, Sungjoo Yoo, Junwhan Ahn, 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

An efficient algorithm for isomorphism-aware custom instruction identification for extensible processors

Kiyoung Choi, Junwhan Ahn, Junwhan Ahn, 2011, 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

A Novel Self-Timed Ring Structure for SRT Division

Kiyoung Choi, Ki Jong Lee, Dong Wan Shin, 1996 .

A deadlock-free routing algorithm requiring no virtual channel on 3D-NoCs with partial vertical connections

Kiyoung Choi, Jinho Lee, 2013, 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS).

An energy-efficient random number generator for stochastic circuits

Kiyoung Choi, Jongeun Lee, Kyounghoon Kim, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

Design of a Synthesizable RISC Processor

Kiyoung Choi, Imyong Lee, Sungyeum Kim, 2004 .

Area-efficient buffer binding based on a novel two-port FIFO structure

Kiyoung Choi, Kyoungseok Rha, 2001, CODES '01.

Scheduler implementation in MP SoC design

Ahmed Amine Jerraya, Kiyoung Choi, Sungjoo Yoo, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Network Recasting: A Universal Method for Network Architecture Transformation

Kiyoung Choi, Joonsang Yu, Sungbum Kang, 2019, AAAI.

An RRAM-based Analog Neuron Design for the Weighted Spiking Neural network

Kiyoung Choi, Jaehyun Kim, Chaeun Lee, 2019, 2019 International SoC Design Conference (ISOCC).

Dynamic clock synchronization scheme between voltage domains in multi-core architecture

Sang-Heon Lee, Kiyoung Choi, Soojung Ryu, 2016, 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

Acceleration of DNN Backward Propagation by Selective Computation of Gradients

Kiyoung Choi, Joonsang Yu, Gunhee Lee, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Training Neural Networks with Low Precision Dynamic Fixed-Point

Kiyoung Choi, Gunhee Lee, Hanmin Park, 2018, 2018 IEEE 36th International Conference on Computer Design (ICCD).

SAT-based state encoding for peak current Minimization

Kiyoung Choi, Yongho Lee, Taewhan Kim, 2009, 2009 International SoC Design Conference (ISOCC).

Automatic mapping of control-intensive kernels onto coarse-grained reconfigurable array architecture with speculative execution

Kiyoung Choi, Kyungwook Chang, Ganghee Lee, 2010, 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW).

Aging Compensation With Dynamic Computation Approximation

Kiyoung Choi, Andreas Gerstlauer, Jorg Henkel, 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model

Kiyoung Choi, Sungjoo Yoo, Sunghyun Lee, 2002, ISLPED '02.

Towards optimal adaptive routing in 3D NoC with limited vertical bandwidth

Kiyoung Choi, Jinho Lee, Gunhee Lee, 2013, NoCArc '13.

Configurable range memory for effective data reuse on programmable accelerators

Kiyoung Choi, Jongeun Lee, Jong Kyung Paek, 2014, TODE.

Partial bus-invert coding for power optimization of system level bus

Kiyoung Choi, Soo-Ik Chae, Youngsoo Shin, 1998, ISLPED '98.

Compression of Simulation Results by Sampling

Kiyoung Choi, Taekyoon Ahn, 1996 .

Communication Architecture Synthesis of Cascaded Bus Matrix

Kiyoung Choi, Sungjoo Yoo, Dongwook Lee, 2007, 2007 Asia and South Pacific Design Automation Conference.

High-level synthesis with distributed controller for fast timing closure

Kiyoung Choi, Seokhyun Lee, 2011, ICCAD 2011.

Multi-codec variable length decoder design with configurable processor

Kiyoung Choi, HyoukJoong Lee, 2008, 2008 International SoC Design Conference.

An FPGA implementation of high-throughput key-value store using Bloom filter

Kiyoung Choi, Jae Min Cho, 2014, Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test.

Hardware-software codesign of resource-constrained real-time systems

Kiyoung Choi, Seongsoo Hong, Sungjoo Yoo, 1996, Proceedings of 3rd International Workshop on Real-Time Computing Systems and Applications.

A new approach to binarizing neural networks

Kiyoung Choi, Joonsang Yu, Jongeun Lee, 2016, 2016 International SoC Design Conference (ISOCC).

Memory and architecture exploration with thread shifting for multithreaded processors in embedded systems

Kiyoung Choi, Mary Kiemb, 2004, CASES '04.

GUEST EDITORS' INTRODUCTION - Special Section on Hardware Description Languages

Kiyoung Choi, Kiyoung Choi, 1998 .

Configurable Processors for Embedded Computing

Kiyoung Choi, Nikil D. Dutt, 2003, Computer.

Dynamic error tracking and supply voltage adjustment for low power

Kiyoung Choi, Pierre Nicolas-Nicolaz, 2015, 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

PIM-enabled instructions: A low-overhead, locality-aware processing-in-memory architecture

Kiyoung Choi, Onur Mutlu, Sungjoo Yoo, 2015, 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA).

Memory-Centric Communication Architecture for Reconfigurable Computing

Kiyoung Choi, Kyungwook Chang, 2010, ARC.

Enforcing Schedulability of Multi-Task Systems by Hardware-Software Codesign

Kiyoung Choi, Youngsoo Shin, Youngsoo Shin, 1997, CODES.

Exploiting New Interconnect Technologies in On-Chip Communication

Kiyoung Choi, John Kim, Gabriel H. Loh, 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space Exploration

Kiyoung Choi, Yongjin Ahn, Ganghee Lee, 2007, 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation.

Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAM

Kiyoung Choi, Junwhan Ahn, Woong Seo, 2015, 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

Low power self-timed Radix-2 division (poster session)

Kiyoung Choi, Jae-Hee Won, 2000, ISLPED '00.

Low power high level synthesis by increasing data correlation

Kiyoung Choi, Dongwan Shin, 1997, ISLPED '97.

Resource sharing and pipelining in coarse-grained reconfigurable architecture for domain-specific optimization

Kiyoung Choi, Yoonjin Kim, Mary Kiemb, 2005, Design, Automation and Test in Europe.

Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks

Kiyoung Choi, Jungki Kim, Joonsang Yu, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Hardware synthesis for stack type partitioned-bus architecture

Kiyoung Choi, Young-Hyun Jun, Kisun Kim, 1999, ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).

Pipelining with common operands for power-efficient linear systems

Kiyoung Choi, Dongwan Shin, Daehong Kim, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Synthesis of Instruction Sets for High-Performance and Energy-Efficient ASIP

Kiyoung Choi, Nikil Dutt, Jongeun Lee, 2007 .

Leveraging parallelism in the presence of control flow on CGRAs

Kiyoung Choi, Kyuseung Han, Jihyun Ryoo, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

Active Memory Processor for Network-on-Chip-Based Architecture

Kiyoung Choi, Sungjoo Yoo, Jun-hee Yoo, 2012, IEEE Transactions on Computers.

Performance-driven high-level synthesis with bit-level chaining andclock selection

Kiyoung Choi, Sanghun Park, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

SoCDAL: System-on-chip design AcceLerator

Kiyoung Choi, Hyunjik Song, Yongjin Ahn, 2008, TODE.

Reduction of bus transitions with partial bus-invert coding

Kiyoung Choi, Soo-Ik Chae, Youngsoo Shin, 1998 .

Approximate de-randomizer for stochastic circuits

Kiyoung Choi, Jongeun Lee, Kyounghoon Kim, 2015, 2015 International SoC Design Conference (ISOCC).

Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures

Kiyoung Choi, Nikil D. Dutt, Jongeun Lee, 2008, Int. J. Embed. Syst..

Library-based Mapping of Application to Reconfigurable Array Architecture

Kiyoung Choi, Kyuseung Han, 2009 .

AN EFFICIENT VLSI ARCHITECTURE FOR LEMPEL-ZIV-BASED DATA COMPRESSION

Kiyoung Choi, Kyuseok Kim, Yongjoo Kim, 1995 .

Scheduling-based code size reduction in processors with indirect addressing mode

Kiyoung Choi, Jihong Kim, Sungtaek Lim, 2001, CODES '01.

Reconfigurable ALU Array Architecture with Conditional Execution

Kiyoung Choi, Jongeun Lee, Yunjin Kim, 2004 .

Energy-efficient partitioning of hybrid caches in multi-core architecture

Kiyoung Choi, Dongwoo Lee, 2014, 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC).

Compilation approach for coarse-grained reconfigurable architectures

Kiyoung Choi, Nikil D. Dutt, Jongeun Lee, 2003, IEEE Design & Test of Computers.

Performance-driven scheduling with bit-level chaining

Kiyoung Choi, Sanghun Park, 1999, DAC '99.

Low Runtime-Overhead Software Synthesis for Communicating Concurrent Processes

Nacer-Eddine Zergainoh, Ahmed Amine Jerraya, Kiyoung Choi, 2007, 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07).

A formal approach toward developing an equivalent circuit for high-speed coupled interconnects with intermediate ground insertion

Kiyoung Choi, Rohit Sharma, Kiyoung Choi, 2010, 2nd Asia Symposium on Quality Electronic Design (ASQED).

Efficient prototyping system based on incremental design and module-by-module verification

Kiyoung Choi, Youngsoo Shin, Jae-Hee Won, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

Compiling control-intensive loops for CGRAs with state-based full predication

Kiyoung Choi, Jongeun Lee, Kyuseung Han, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

An integrated hardware-software cosimulation environment with automated interface generation

Kiyoung Choi, Kyuseok Kim, Yongjoo Kim, 1996, Proceedings Seventh IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype.

Fast hardware-software coverification by optimistic execution of real processor

Kiyoung Choi, Sungjoo Yoo, Jongeun Lee, 2000, DATE '00.

GPU-Based Acceleration of Quantum-Inspired Evolutionary Algorithm

Kiyoung Choi, Hanmin Park, Ji-Hyun Ryoo, 2012 .

3D network-on-chip with wireless links through inductive coupling

Kiyoung Choi, Jung Ho Ahn, Jinho Lee, 2011, 2011 International SoC Design Conference.

Energy Efficient Analog Synapse/Neuron Circuit for Binarized Neural Networks

Kiyoung Choi, Jaehyun Kim, Chaeun Lee, 2018, 2018 International SoC Design Conference (ISOCC).

Isomorphism-Aware Identification of Custom Instructions With I/O Serialization

Kiyoung Choi, Junwhan Ahn, Junwhan Ahn, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Thread-based software synthesis for embedded system design

Kiyoung Choi, Youngsoo Shin, 1996, Proceedings ED&TC European Design and Test Conference.

Dirty-Block Tracking in a Direct-Mapped DRAM Cache with Self-Balancing Dispatch

Sang-Heon Lee, Kiyoung Choi, Dongwoo Lee, 2017, ACM Trans. Archit. Code Optim..

Efficient instruction encoding for automatic instruction set design of configurable ASIPs

Kiyoung Choi, Nikil D. Dutt, Jongeun Lee, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

Implementation of floating-point operations for 3D graphics on a coarse-grained reconfigurable architecture

Kiyoung Choi, V. K. Prasad Arava, Manhwee Jo, 2007, SoCC.

Write intensity prediction for energy-efficient non-volatile caches

Kiyoung Choi, Sungjoo Yoo, Junwhan Ahn, 2013, International Symposium on Low Power Electronics and Design (ISLPED).

Effective synthesis algorithm for partitioned bus architecture

Kiyoung Choi, Jinhwan Jeon, 1999 .

QoS-aware dynamic power management for coarse-grained reconfigurable architecture

Kiyoung Choi, Nikil Dutt, Yongjin Ahn, 2009, 2009 International Conference on Field-Programmable Technology.

IEEE Journal on Emerging and Selected Topics in Circuits and Systems information for authors

Jason Cong, Ronald Tetzlaff, Gert Cauwenberghs, 2018, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Fast Simulation Method for Analog Deep Binarized Neural Networks

Kiyoung Choi, Jihun Kim, Jaehyun Kim, 2019, 2019 International SoC Design Conference (ISOCC).

Scalable stochastic-computing accelerator for convolutional neural networks

Kiyoung Choi, Dong Nguyen, Jongeun Lee, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

Worst case execution time analysis for synthesized hardware

Kiyoung Choi, Eui-Young Chung, Kyu-Myung Choi, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Efficient VLSI architecture for lossless data compression

Kiyoung Choi, Young-Kook Kim, Kyuwoong Kim, 1995 .

Coarse-grained reconfigurable architecture for multiple application domains: a case study

Kiyoung Choi, Kyuseung Han, Manhwee Jo, 2009, ICHIT '09.

Deflection routing in 3D network-on-chip with limited vertical bandwidth

Kiyoung Choi, Jinho Lee, Dongwook Lee, 2013, TODE.

Proceedings of the 2008 Asia and South Pacific Design Automation Conference

Soonhoi Ha, Kiyoung Choi, Chong-Min Kyung, 2008, ASP-DAC 2008.

A Memetic Quantum-Inspired Evolutionary Algorithm for circuit bipartitioning problem

Kiyoung Choi, Dongwoo Lee, Junwhan Ahn, 2012, 2012 International SoC Design Conference (ISOCC).

Rate assignment for embedded reactive real-time systems

Kiyoung Choi, Youngsoo Shin, 1998, Proceedings. 24th EUROMICRO Conference (Cat. No.98EX204).

DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture

Kiyoung Choi, Sungjoo Yoo, Junwhan Ahn, 2014, 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA).

An Integrated Cosimulation Environment for Heterogeneous Systems Prototyping

Kiyoung Choi, Kyuseok Kim, Yongjoo Kim, 1998, Des. Autom. Embed. Syst..

Latency minimisation by system clock optimisation

Kiyoung Choi, Sanghun Park, 1998 .

A Transformation Technique for power-conscious High Level Synthesis

Kiyoung Choi, Daehong Kim, 1996 .

Thor user''s manual: library functions

Kiyoung Choi, Robert Alverson, Tom Blank, 1988 .

Design of a coarse-grained reconfigurable architecture with floating-point support and comparative study

Kiyoung Choi, Dongwook Lee, Kyuseung Han, 2014, Integr..

Accurate and Efficient Stochastic Computing Hardware for Convolutional Neural Networks

Kiyoung Choi, Joonsang Yu, Jongeun Lee, 2017, 2017 IEEE International Conference on Computer Design (ICCD).

Design verification by concurrent simulation and automatic comparison

Kiyoung Choi, Taekyoon Ahn, 1997, Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg.

An Efficient Simulation Environment and Simulation Techniques for Bluetooth Device Design

Kiyoung Choi, Sungjoo Yoo, Soo-Ik Chae, 2003, Des. Autom. Embed. Syst..

Topology/Floorplan/Pipeline Co-Design of Cascaded Crossbar Bus

Kiyoung Choi, Sungjoo Yoo, Jun-hee Yoo, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design and Evaluation of a Coarse-Grained Reconfigurable Architecture

Kiyoung Choi, Hyunjik Song, Yoonjin Kim, 2004 .

Communication architecture design for reconfigurable multimedia SoC platform

Kiyoung Choi, Yongjin Ahn, Ganghee Lee, 2010, Des. Autom. Embed. Syst..

Low power self-timed floating-point divider in 0.25um technology

Kiyoung Choi, Jae-Hee Won, 2000, Proceedings of the 26th European Solid-State Circuits Conference.

Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip

Nacer-Eddine Zergainoh, Ahmed Amine Jerraya, Kiyoung Choi, 2007, Des. Autom. Embed. Syst..

Fast cycle-approximate MPSoC simulation based on synchronization time-point prediction

Kiyoung Choi, Sungjoo Yoo, Jinyong Jung, 2007, Des. Autom. Embed. Syst..

New address generation scheme for memory-based FFT processor using multiple radix-2 butterflies

Kiyoung Choi, Jaehyun Baek, 2008, 2008 International SoC Design Conference.

Instruction set synthesis with efficient instruction encoding for configurable processors

Kiyoung Choi, Nikil D. Dutt, Jongeun Lee, 2007, TODE.

A host-accelerator communication architecture design for efficient binary acceleration

Kiyoung Choi, Kyuseung Han, Yangsu Kim, 2011, 2011 International SoC Design Conference.

Architectures and algorithms for user customization of CNNs

Soonhoi Ha, Kiyoung Choi, Bernhard Egger, 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

Partial bus-invert coding for power optimization of application-specific systems

Kiyoung Choi, Soo-Ik Chae, Youngsoo Shin, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Guest Editorial for Special Issue on Emerging Memory Technologies - Modeling, Design, and Applications for Multi-Scale Computing

Yiran Chen, Kiyoung Choi, Weisheng Zhao, 2015, IEEE Transactions on Multi-Scale Computing Systems.

THOR: Orchestrated thermal management of cores and networks in 3D many-core architectures

Kiyoung Choi, Jinho Lee, Junwhan Ahn, 2015, The 20th Asia and South Pacific Design Automation Conference.

Power-conscious high level synthesis using loop folding

Kiyoung Choi, Daehong Kim, 1997, DAC.

Concept-aware ensemble system for pedestrian detection

Kiyoung Choi, Kyounghoon Kim, Helin Lin, 2014, 2014 IEEE Intelligent Vehicles Symposium Proceedings.

An Efficient Self-Timed Divider

Kiyoung Choi, Jun Woo Kang, 1993 .

Autonomic Diffusive Load Balancing on Many-Core Architecture Using Simulated Annealing

Kiyoung Choi, Hyunjik Song, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

VCAM: Variation Compensation through Activation Matching for Analog Binarized Neural Networks

Kiyoung Choi, Jaehyun Kim, Jihun Kim, 2019, 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Power-conscious Scheduling for Real-time Embedded Systems Design

Kiyoung Choi, Takayasu Sakurai, Youngsoo Shin, 2001, VLSI Design.

High-level synthesis under multi-cycle interconnect delay

Kiyoung Choi, Dongwan Shin, Jinhwan Jeon, 2001, ASP-DAC '01.

ODALRISC: A small, low power, and configurable 32-bit RISC processor

Kiyoung Choi, Dongwook Lee, Imyong Lee, 2008, 2008 International SoC Design Conference.

Energy-efficient partitioning of hybrid caches in multi-core architecture

Kiyoung Choi, Dongwoo Lee, 2014, VLSI-SoC.

A new cost model for high-level power optimization and its application

Ki-Hyun Kim, Kiyoung Choi, Taekyoon Ahn, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

An algorithm for mapping loops onto coarse-grained reconfigurable architectures

Kiyoung Choi, Nikil D. Dutt, Jongeun Lee, 2003, LCTES '03.

Reconfigurable Multi-Input Adder Design for Deep Neural Network Accelerators

Kiyoung Choi, Hossein Moradian, Sujeong Jo, 2018, 2018 International SoC Design Conference (ISOCC).

Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture

Kiyoung Choi, Nikil D. Dutt, Ganghee Lee, 2010, ARC.

Interleaving partial bus-invert coding for low power reconfiguration of FPGAs

Kiyoung Choi, Sungjoo Yoo, 1999, ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).

Self-timed statistical carry lookahead adder using multiple-output DCVSL

Kiyoung Choi, Jae-Hee Won, 1999, ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).

Guest Editorial New Interconnect Technologies in On-Chip Communication

Kiyoung Choi, John Kim, Gabriel H. Loh, 2012, IEEE J. Emerg. Sel. Topics Circuits Syst..

Benzene

Kiyoung Choi, Soojung Ryu, Junwhan Ahn, 2018, ACM Trans. Archit. Code Optim..

Incremental-in-time algorithm for digital simulation

Kiyoung Choi, Sun Young Hwang, Tom Blank, 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

Software-Level Approaches for Tolerating Transient Faults in a Coarse-GrainedReconfigurable Architecture

Kiyoung Choi, Kyuseung Han, Ganghee Lee, 2014, IEEE Transactions on Dependable and Secure Computing.

Power optimization of real-time embedded systems on variable speed processors

Kiyoung Choi, Takayasu Sakurai, Youngsoo Shin, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Buffered compares: Excavating the hidden parallelism inside DRAM architectures with lightweight logic

Kiyoung Choi, Jung Ho Ahn, Jinho Lee, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Power-Efficient Predication Techniques for Acceleration of Control Flow Execution on CGRA

Kiyoung Choi, Junwhan Ahn, Kyuseung Han, 2013, TACO.

Automatic Generation of Transaction Level Code for Fast SoC Design Space Exploration

Kiyoung Choi, Yongjin Ahn, Ganghee Lee, 2006 .

Leakage power reduction of functional units in processors having zero-overhead loop counter

Kiyoung Choi, Jinho Lee, Jong Kyung Paek, 2009, 2009 International SoC Design Conference (ISOCC).

Low power self-timed radix-2 division

Kiyoung Choi, Jae-Hee Won, 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

CRM: Configurable Range Memory for Fast Reconfigurable Computing

Kiyoung Choi, Jongeun Lee, Jong Kyung Paek, 2011, 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum.

ComPEND: Computation Pruning through Early Negative Detection for ReLU in a Deep Neural Network Accelerator

Kiyoung Choi, Dongwoo Lee, Sungbum Kang, 2018, ICS.

ExtraV: Boosting Graph Processing Near Storage with a Coherent Accelerator

Kiyoung Choi, H. Peter Hofstee, Heesu Kim, 2017, Proc. VLDB Endow..

Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis

Jürgen Teich, Soonhoi Ha, Kiyoung Choi, 2007 .

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004

Kiyoung Choi, Rajiv V. Joshi, Vivek Tiwari, 2004, ISLPED.

Incremental training of CNNs for user customization: work-in-progress

Soonhoi Ha, Kiyoung Choi, Bernhard Egger, 2017, CASES.

Instruction set synthesis with efficient instruction encoding for configurable processors

Kiyoung Choi, Nikil D. Dutt, Jong-Eun Lee, 2007, TODE.

Fast Prototyping of an IS-95 CDMA Cellular Phone : a Case Study

Kiyoung Choi, Jongeun Lee, Sungjoo Yoo, 1999 .

AIM

Kiyoung Choi, Sungjoo Yoo, Junwhan Ahn, 2016 .

Work-in-progress: incremental training of CNNs for user customization

Soonhoi Ha, Kiyoung Choi, Bernhard Egger, 2017, 2017 International Conference on Compilers, Architectures and Synthesis For Embedded Systems (CASES).

Software synthesis through task decomposition by dependency analysis

Kiyoung Choi, Youngsoo Shin, 1996, Proceedings of International Conference on Computer Aided Design.

A scalable processing-in-memory accelerator for parallel graph processing

Kiyoung Choi, Onur Mutlu, Sungpack Hong, 2015, 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA).

Power minimization of functional units partially guarded computation

Kiyoung Choi, Jinhwan Jeon, Junghwan Choi, 2000, ISLPED '00.

Performance estimation of multiple-cache IP-based systems: case study of an interdependency problem and application of an extended shared memory model

Kiyoung Choi, Sungjoo Yoo, Jinyong Jung, 2000, CODES '00.

Mapping and Scheduling of Tasks and Communications on Many-Core SoC Under Local Memory Constraint

Kiyoung Choi, Jung Ho Ahn, Soojung Ryu, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Narrow bus encoding for low power systems

Kiyoung Choi, Youngsoo Shin, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

REDELF: An Energy-Efficient Deadlock-Free Routing for 3D NoCs with Partial Vertical Connections

Kiyoung Choi, Jinho Lee, Kyungsu Kang, 2015, ACM J. Emerg. Technol. Comput. Syst..

LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology

Kiyoung Choi, Junwhan Ahn, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Tapered-Ratio Compression for Residual Network

Kiyoung Choi, Joonsang Yu, Sungbum Kang, 2018, 2018 International SoC Design Conference (ISOCC).

GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descent

Kiyoung Choi, Hyuk-Jae Lee, Soojung Ryu, 2021, 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA).

Automatic Instruction Set Design Through Efficient Instruction Encoding for Application-Specific Processors

Kiyoung Choi, Nikil D. Dutt, Jong-eun Lee, 2003 .

Partial bus-invert coding for power optimization of system level bus

Kiyoung Choi, Soo-Ik Chae, Youngsoo Shin, 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

Schedulability-driven performance analysis of multiple mode embedded real-time systems

Kiyoung Choi, Youngsoo Shin, Youngsoo Shin, 2000, Proceedings 37th Design Automation Conference.

Benzene

Kiyoung Choi, Soojung Ryu, Junwhan Ahn, 2018, Report on carcinogens : carcinogen profiles.

Partitioned-bus architecture synthesis based on data transfer model

Kiyoung Choi, Seungyoul Lee, .

Scheduling-based code size reduction in processors with indirect addressing mode

Kiyoung Choi, Sungtaek Lim, Jihong Kim, 2001, Ninth International Symposium on Hardware/Software Codesign. CODES 2001 (IEEE Cat. No.01TH8571).

Java-Based Programmable Networked Embedded System Architecture with Multiple Application Support

Kiyoung Choi, Seongsoo Hong, Sunghyun Lee, .

AIM

Kiyoung Choi, Sungjoo Yoo, Junwhan Ahn, 2016 .

Scheduling and timing analysis of HW/SW on-chip communication in MP SoC design

Kiyoung Choi, Sungjoo Yoo, Youngchul Cho, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

An adaptive routing algorithm for 3D mesh NoC with limited vertical bandwidth

Kiyoung Choi, Mingyang Zhu, Jinho Lee, 2012, 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC).

Low power high level synthesis by increasing data correlation

Kiyoung Choi, Dongwan Shin, 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model

Kiyoung Choi, Sungjoo Yoo, Sunghyun Lee, 2002, Proceedings of the International Symposium on Low Power Electronics and Design.

Modified half rail differential logic for reduced internal logic swing

Kiyoung Choi, Jae-Hee Won, 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

Performance-driven scheduling with bit-level chaining

Kiyoung Choi, Sanghun Park, 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

Ecient Prototyping System Based on Incremental Design and Module-by-module Verication

Kiyoung Choi, Youngsoo Shin, Yongjoo Kim, 1995 .

DOMAIN-SPECIFIC OPTIMIZATION OF RECONFIGURABLE ARRAY ARCHITECTURE

Kiyoung Choi, Yoonjin Kim, Chulsoo Park, 2006 .