Taewhan Kim

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Algorithms for Combined Inter- and Intra-Task Dynamic Voltage Scaling

Taewhan Kim, Hyungjung Seo, Jaewon Seo, 2012, Comput. J..

Arithmetic optimization using carry-save-adders

Taewhan Kim, Steven W. K. Tjiang, William Jao, 1998, DAC.

Thermal sensor allocation and placement for reconfigurable systems

Taewhan Kim, Bontae Koo, Nak-Woong Eum, 2009, TODE.

Die matching algorithm for enhancing parametric yield of 3D ICs

Taewhan Kim, Sangdo Park, 2012, 2012 International SoC Design Conference (ISOCC).

Timing Analysis and Optimization Based on Flexible Flip-Flop Timing Model

Taewhan Kim, Jeongwoo Heo, 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Memory allocation and mapping in high-level synthesis - an integrated approach

Taewhan Kim, Preeti Ranjan Panda, Jaewon Seo, 2003, IEEE Trans. Very Large Scale Integr. Syst..

An Accurate Exploration of Timing and Area Trade-Offs in Arithmetic Optimization Using Carry-Save-Adders

Taewhan Kim, Youngtae Kim, 2000, J. Circuits Syst. Comput..

A timing-driven synthesis of arithmetic circuits using carry-save-adders

Taewhan Kim, Junhyung Um, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

High-level synthesis for low power based on network flow method

Taewhan Kim, Chun-Gi Lyuh, Taewhan Kim, 2003, IEEE Trans. Very Large Scale Integr. Syst..

Cohesive techniques for cell layout optimization supporting 2D metal-1 routing completion

Taewhan Kim, Kyu-Myung Choi, Kyeongrok Jo, 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

Hybrid asynchronous circuit generation amenable to conventional EDA flow

Taewhan Kim, Heechun Park, 2019, Integr..

Allocation and optimization of Post-silicon tunable buffers in TSV based heterogeneous 3D ICs

Taewhan Kim, Sangdo Park, Jeongwoo Heo, 2014, 2014 International SoC Design Conference (ISOCC).

Resource Allocation and Design Techniques of Prebond Testable 3-D Clock Tree

Taewhan Kim, Tak-Yung Kim, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Adjustable Delay Buffer Allocation under Useful Clock Skew Scheduling

Taewhan Kim, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems

Taewhan Kim, Deokjin Joo, Taewhan Kim, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Clock buffer polarity assignment considering the effect of delay variations

Taewhan Kim, Minseok Kang, Taewhan Kim, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

An accurate evaluation of routing density for symmetrical FPGAs

Taewhan Kim, Chong-Min Kyung, Nak-Woong Eum, 2001, GLSVLSI '01.

A New Virtual ARM Platform with Improved Run Time Behavior and Debugging Capability

Taewhan Kim, Youngho Ahn, Ki-Seok Chung, 2009 .

A static estimation technique of power sensitivity in logic circuits

Taewhan Kim, Chien-Liang Liu, Ki-Seok Chung, 2001, DAC '01.

Thermal-Aware High-Level Synthesis Based on Network Flow Method

Taewhan Kim, Ki-Seok Chung, Pilok Lim, 2009, J. Circuits Syst. Comput..

An optimal algorithm for allocation, placement, and delay assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs

Taewhan Kim, Kyoung-Hwan Lim, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

A stepwise refinement synthesis of digital systems for testability enhancement

Taewhan Kim, Kwan Soo Chung, C. L. Liu, 1999 .

Memory exploration utilizing scheduling effects in high-level synthesis

Taewhan Kim, Jaewon Seo, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Energy-optimal algorithm for dynamic voltage scaling with non-convex power functions

Taewhan Kim, Juyeon Kim, 2014, 2014 International SoC Design Conference (ISOCC).

DC-DC converter-aware power management for battery-operated embedded systems

Taewhan Kim, Naehyuck Chang, Yongseok Choi, 2005, Proceedings. 42nd Design Automation Conference, 2005..

A non-zero delay model for glitch analysis in logic circuits

Taewhan Kim, C. L. Liu, Ki-Seok Chung, 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

A HW/SW Partitioner for Multi-Mode Multi-Task Embedded Applications

Taewhan Kim, Young-Jun Kim, Taewhan Kim, 2006, J. VLSI Signal Process..

Circuit optimization using carry-save-adder cells

Taewhan Kim, Steven W. K. Tjiang, William Jao, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Binding Algorithm for Power Optimization Based on Network Flow Method

Taewhan Kim, Yoonseo Choi, 2002, J. Circuits Syst. Comput..

Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization

Taewhan Kim, Hochang Jang, 2009, 2009 46th ACM/IEEE Design Automation Conference.

Memory access driven storage assignment for variables in embedded system design

Taewhan Kim, Yoonseo Choi, 2004, ASP-DAC.

Energy-optimal dynamic voltage scaling in multicore platforms with reconfigurable power distribution network

Taewhan Kim, Juyeon Kim, 2018, 2018 19th International Symposium on Quality Electronic Design (ISQED).

Power-aware inductor analysis in resonant clock networks

Taewhan Kim, Minseok Kang, Seyong Ahn, 2013, 2013 International SoC Design Conference (ISOCC).

Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modes

Taewhan Kim, Deokjin Joo, Juyeon Kim, 2016, Integr..

Address Code Optimization Exploiting Code Scheduling in DSP Applications

Taewhan Kim, Zhenmin Li, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Clock buffer polarity assignment utilizing useful clock skews for power noise reduction

Taewhan Kim, Deokjin Joo, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

Clock tree synthesis with pre-bond testability for 3D stacked IC Designs

Taewhan Kim, Tak-Yung Kim, 2010, Design Automation Conference.

Thermal-aware high-level synthesis based on network flow method

Taewhan Kim, Pilok Lim, 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

Synthesis and Optimization of Combinational Interface Circuits

Taewhan Kim, Rajesh K. Gupta, C. L. Liu, 2002, J. VLSI Signal Process..

Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization

Taewhan Kim, Yesin Ryu, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

Tight integration of timing-driven synthesis and placement of parallel multiplier circuits

Taewhan Kim, Keoncheol Shin, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Application-Driven Low-Power Techniques Using Dynamic Voltage Scaling

Taewhan Kim, 2006, 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'06).

Edge layer embedding algorithm for mitigating on-package variation in 3D clock tree synthesis

Taewhan Kim, Sangdo Park, Taewhan Kim, 2014, Integr..

A practical approach to the synthesis of arithmetic circuits usingcarry-save-adders

Taewhan Kim, Junhyung Um, Taewhan Kim, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Integrated Resource Allocation and Binding in Clock Mesh Synthesis

Taewhan Kim, Minseok Kang, Taewhan Kim, 2014, TODE.

Design Methodology for TSV-Based 3D Clock Networks

Taewhan Kim, Heechun Park, 2017 .

HW/SW partitioning techniques for multi-mode multi-task embedded applications

Taewhan Kim, Young-Jun Kim, Taewhan Kim, 2006, GLSVLSI '06.

Power Saving by Task-Level Dynamic Voltage Scaling

Taewhan Kim, 2012, Handbook of Energy-Aware and Green Computing.

Comments on the Originality of the Paper, ``The Integrated Scheduling and Allocation of High-Level Test synthesis''

Taewhan Kim, 1999 .

An accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save adder cells

Taewhan Kim, Young-Tae Kim, 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

G-vector: a new model for glitch analysis

Taewhan Kim, Ki-Seok Chung, Chun-Liang Lin, 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).

An energy-optimal algorithm for temperature-aware idle time distribution considering mode transition overhead

Taewhan Kim, Sangdo Park, 2011, 2011 International SoC Design Conference.

Clock buffer polarity assignment under useful skew constraints

Taewhan Kim, Deokjin Joo, 2017, Integr..

Statistical Viability Analysis for Detecting False Paths Under Delay Variation

Taewhan Kim, Jongyoon Jung, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Layout-driven resource sharing in high-level synthesis

Jae-Hoon Kim, Taewhan Kim, Junhyung Um, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

Timing variation-aware high level synthesis: Current results and research challenges

Taewhan Kim, Jongyoon Jung, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

Loosely coupled multi-bit flip-flop allocation for power reduction

Taewhan Kim, Hyoungseok Moon, 2017, Integr..

Timing variation-aware task scheduling and binding for MPSoC

Taewhan Kim, HaNeul Chon, Taewhan Kim, 2009, 2009 Asia and South Pacific Design Automation Conference.

Structure optimizations of neuromorphic computing architectures for deep neural network

Taewhan Kim, Heechun Park, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits

Taewhan Kim, Deog-Kyoon Jeong, Yongho Lee, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

A complete model for glitch analysis in logic circuits

Taewhan Kim, C. L. Liu, Ki-Seok Chung, 2000, Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541).

An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem

Taewhan Kim, Deokjin Joo, Juyeon Kim, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Post-silicon tuning aware wafer matching algorithm for 3d integration of ICs

Taewhan Kim, Sangdo Park, 2014, 2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS).

A systematic IP and bus subsystem modeling for platform-based system design

Taewhan Kim, Sungpack Hong, Jeong-Taek Kong, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Design Methodologies for Reliable Clock Networks

Taewhan Kim, Minseok Kang, Deokjin Joo, 2012, J. Comput. Sci. Eng..

Autonomous temperature control technique in VLSI circuits through logic replication

Taewhan Kim, Benjamin Carrión Schäfer, 2009, IET Comput. Digit. Tech..

A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation

Taewhan Kim, Chong-Min Kyung, Nak Woong Eum, 2001, ICCAD.

Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture

Taewhan Kim, Kyoung-Hwan Lim, YongHwan Kim, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Post Silicon Management of On-Package Variation Induced 3D Clock Skew

Taewhan Kim, Tak-Yung Kim, Taewhan Kim, 2012 .

Timing variation-aware high-level synthesis

Taewhan Kim, Jongyoon Jung, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

High-Level Synthesis using Carry-Save-Adders

Taewhan Kim, Dongwook Lee, 2004 .

High-level TSV resource sharing and optimization for TSV based 3D IC designs

Taewhan Kim, Byunghyun Lee, 2013, 2013 IEEE International SOC Conference.

WaveMin: A fine-grained clock buffer polarity assignment combined with buffer sizing

Taewhan Kim, Deokjin Joo, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures

Taewhan Kim, Youngsoo Shin, Seungwhun Paik, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications

Taewhan Kim, Nikil D. Dutt, Jaewon Seo, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designs

Taewhan Kim, Kitae Park, Geunho Kim, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Synthesis and exploration of clock spines

Taewhan Kim, Youngchan Kim, 2018, IET Comput. Digit. Tech..

Grey-level context-driven histogram equalisation

Taewhan Kim, Hyoungjun Jeon, Taewhan Kim, 2016, IET Image Process..

Optimal intratask dynamic voltage-scaling technique and its practical extensions

Joonwon Lee, Taewhan Kim, Jaewon Seo, 2006, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Technique for Transition Energy-Aware Dynamic Voltage Assignment

Taewhan Kim, Jong-U. Shin, 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

Memory access scheduling and binding considering energy minimization in multi-bank memory systems

Taewhan Kim, Chun-Gi Lyuh, Taewhan Kim, 2004, Proceedings. 41st Design Automation Conference, 2004..

Timing variation-aware high-level synthesis considering accurate yield computation

Taewhan Kim, Jongyoon Jung, 2009, 2009 IEEE International Conference on Computer Design.

Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design

Taewhan Kim, Junhyung Um, 2003, ICCAD 2003.

Context-driven hybrid image inpainting

Taewhan Kim, Lu Cai, Taewhan Kim, 2015, IET Image Process..

Task-Level Dynamic Voltage Scaling for Embedded System Design: Recent Theoretical Results

Taewhan Kim, 2010, J. Comput. Sci. Eng..

Address assignment combined with scheduling in DSP code generation

Taewhan Kim, Yoonseo Choi, 2002, DAC '02.

DC–DC Converter-Aware Power Management for Low-Power Embedded Systems

Taewhan Kim, Naehyuck Chang, Yongseok Choi, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design

Taewhan Kim, Junhyung Um, 2003, ICCAD.

Bounded skew clock routing for 3D stacked IC designs: Enabling trade-offs between power and clock skew

Taewhan Kim, Tak-Yung Kim, 2010, International Conference on Green Computing.

Design and Algorithm for Clock Gating and Flip-flop Co-optimization

Taewhan Kim, Giyoung Yang, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design

Taewhan Kim, Jungeun Kim, 2005, Proceedings. 42nd Design Automation Conference, 2005..

Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders

Taewhan Kim, Youngtae Kim, 2001, ASP-DAC '01.

Leakage power minimization for the synthesis of parallel multiplier circuits

Taewhan Kim, Keoncheol Shin, 2004, GLSVLSI '04.

Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors

Taewhan Kim, Nam Sung Kim, Jungseob Lee, 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Algorithm for synthesizing design context-aware fast carry-skip adders

Taewhan Kim, Kiyoung Kim, 2012, 17th Asia and South Pacific Design Automation Conference.

Optimal allocation of carry-save-adders in arithmetic optimization

Taewhan Kim, C. L. Liu, Junhyung Um, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Clock skew optimization for maximizing time margin by utilizing flexible flip-flop timing

Taewhan Kim, Hyungjung Seo, Jeongwoo Heo, 2015, Sixteenth International Symposium on Quality Electronic Design.

Profile-based optimal intra-task voltage scheduling for hard real-time applications

Taewhan Kim, Jaewon Seo, Ki-Seok Chung, 2004, Proceedings. 41st Design Automation Conference, 2004..

Fast algorithm of low power image reformation for OLED display

Taewhan Kim, Myung Woo Lee, Taewhan Kim, 2014, Digital Image Processing.

Utilization of carry-save-adders in arithmetic optimization

Taewhan Kim, Junhyung Um, Taewhan Kim, 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).

Logic transformation for low-power synthesis

Sung-Mo Kang, Taewhan Kim, TingTing Hwang, 2002, TODE.

A methodology for verifying memory access protocols in behavioral synthesis

Taewhan Kim, Gernot Koch, Reiner Genevriere, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Bus-invert coding for low-power I/O - a decomposition approach

Taewhan Kim, Sungpack Hong, Unni Narayanan, 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

Tutorials [6 abstracts]

Taewhan Kim, Jerald Yoo, Nathan M. Neihart, 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).

An integrated data path optimization for low power based on network flow method

Taewhan Kim, Chien-Liang Liu, Chun-Gi Lyuh, 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

Switch cell optimization of power-gated modern system-on-chips

Taewhan Kim, Dongyoun Yi, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Session details: Emerging ideas in energy management techniques

Taewhan Kim, Diana Marculescu, Rajesh Gupta, 2005, DAC '05.

An integrated algorithm for incremental data path synthesis

Taewhan Kim, C. L. Liu, 1996, J. VLSI Signal Process..

Algorithm for synthesis and exploration of clock spines

Taewhan Kim, Youngchan Kim, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

Domino logic synthesis based on implication graph

Sung-Mo Kang, Taewhan Kim, C. L. Liu, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Bus Optimization for Low Power in High-Level Synthesis

Taewhan Kim, Sungpack Hong, 2003, J. Circuits Syst. Comput..

Coupling delay optimization by temporal decorrelation using dual threshold voltage technique

Taewhan Kim, Seong-Ook Jung, C. L. Liu, 2003, IEEE Trans. Very Large Scale Integr. Syst..

Post-silicon tunable clock buffer allocation based on fast chip yield computation

Taewhan Kim, Hyungjung Seo, 2014, Fifteenth International Symposium on Quality Electronic Design.

Measurement and comparison of taekwondo and yongmudo turning kick impact force for two target heights.

Sungchul Kang, Taewhan Kim, Insik Shin, 2009, Journal of sports science & medicine.

Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs

Taewhan Kim, Byunghyun Lee, 2014, Integr..

Non-Convex Power Functions

Taewhan Kim, Juyeon Kim, 2014 .

Synthesis for power-aware clock spines

Taewhan Kim, Hyungjung Seo, Minseok Kang, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Utilization of Multiport Memories in Data Path Synthesis

Taewhan Kim, C. L. Liu, Taewhan Kim, 1993, 30th ACM/IEEE Design Automation Conference.

Memory access driven storage assignment for variables in embedded system design

Taewhan Kim, Yoonseo Choi, 2004 .

Resource Sharing Problem of Timing Variation-Aware Task Scheduling and Binding in MPSoC

Taewhan Kim, HaNeul Chon, 2010, Comput. J..

Taewhan Kim, C. L. Liu, Chaeryung Park, 1998, J. VLSI Signal Process..

Synthesis of TSV Fault-Tolerant 3-D Clock Trees

Taewhan Kim, Heechun Park, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Managing clock skews in clock trees with local clock skew requirements using adjustable delay buffers

Taewhan Kim, Deokjin Joo, 2015, 2015 International SoC Design Conference (ISOCC).

Verification of memory access protocols in behavioral synthesis

Taewhan Kim, G. Koch, Reiner Wilhelm Genevriere, 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

Fault coverage and resource analysis for diverse structures of clock TSV fault-tolerant units in 3D ICs

Taewhan Kim, Heechun Park, 2013, 2013 International SoC Design Conference (ISOCC).

A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper)

Taewhan Kim, Junhyung Um, 2000, ASP-DAC.

A router for symmetrical FPGAs based on exact routing density evaluation

Taewhan Kim, Chong-Min Kyung, Nak-Woong Eum, 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

An Integrated Approach to Data Path Synthesis for Low Power

Taewhan Kim, 1999 .

Optimal voltage allocation techniques for dynamically variable voltage processors

Taewhan Kim, Woo-Cheol Kwon, 2003, DAC '03.

Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling

Marios C. Papaefthymiou, Taewhan Kim, Minseok Kang, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Memory Access Driven Memory Layout and Block Replacement Techniques for Compressed Deep Neural Networks

Taewhan Kim, Byungmin Ahn, 2018, 2018 31st IEEE International System-on-Chip Conference (SOCC).

Coupling-aware high-level interconnect synthesis for low power

Taewhan Kim, Chun-Gi Lyuh, Ki-Wook Kim, 2002, ICCAD 2002.

A new approach to the multiport memory allocation problem in data path synthesis

Taewhan Kim, C. L. Liu, Taewhan Kim, 1995, Integr..

Useful clock skew scheduling using adjustable delay buffers in multi-power mode designs

Taewhan Kim, Juyeon Kim, Taewhan Kim, 2015, The 20th Asia and South Pacific Design Automation Conference.

Scheduling and Resource Binding Algorithm Considering Timing Variation

Taewhan Kim, Jongyoon Jung, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Technique for controlling power-mode transition noise in distributed sleep transistor network

Taewhan Kim, Yongho Lee, Taewhan Kim, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Post-Silicon Tuning Based on Flexible Flip-Flop Timing

Taewhan Kim, Hyungjung Seo, Jeongwoo Heo, 2016 .

Coupling-aware high-level interconnect synthesis for low power

Taewhan Kim, Chun-Gi Lyuh, Ki-Wook Kim, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

Ultra low power 2-tier 3D stacked sub-threshold H.264 intra frame encoder

Taewhan Kim, Taesung Kim, Sung Kyu Lim, 2013, 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Memory access driven storage assignment for variables in embedded system design

Taewhan Kim, Yoonseo Choi, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs

Taewhan Kim, Deokjin Joo, Kyoung-Hwan Lim, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Synthesis of resonant clock networks supporting dynamic voltage / frequency scaling

Marios C. Papaefthymiou, Taewhan Kim, Minseok Kang, 2015, The 20th Asia and South Pacific Design Automation Conference.

Resource-constrained low-power bus encoding with crosstalk delay elimination

Taewhan Kim, Meeyoung Cha, Chun-Gi Lyuh, 2002, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits

Taewhan Kim, Junhyung Um, 2001, IEEE Trans. Computers.

Circuit Timing Analysis and Optimization under Flexible Flip-flop Timing Model

Taewhan Kim, Jeongwoo Heo, 2017 .

Layout-driven resource sharing in high-level synthesis

Taewhan Kim, Junhyung Um, Jae-hoon Kim, 2002, ICCAD 2002.

Interconnect and communication synthesis for distributed register-file microarchitecture

Taewhan Kim, Yonghwan Kim, Kyoung-Hwan Lim, 2009, IET Comput. Digit. Tech..

Design and allocation of loosely coupled multi-bit flip-flops for power reduction in post-placement optimization

Taewhan Kim, Hyoungseok Moon, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

Temperature-Aware Compilation for VLIWProcessors

Taewhan Kim, Benjamin Carrión Schäfer, Yongho Lee, 2007, 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007).

Globally Tunable Histogram Equalization for Image Enhancement

Taewhan Kim, Hyoungjun Jeon, 2015 .

Taewhan Kim, C. L. Liu, Chaeryung Park, 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.

Variation-Aware False Path Analysis Based on Statistical Dynamic Timing Analysis

Taewhan Kim, Jongyoon Jung, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Behavioral-level partitioning for low power design in control-dominated application

Taewhan Kim, Chien-Liang Liu, Ki-Seok Chung, 2000, ACM Great Lakes Symposium on VLSI.

G-vector: A New Model for Glitch Analysis in Logic Circuits

Taewhan Kim, C. L. Liu, Ki-Seok Chung, 2001, J. VLSI Signal Process..

Decomposition of Bus-Invert Coding for Low-Power I/O

Taewhan Kim, Sungpack Hong, Unni Narayanan, 2000, J. Circuits Syst. Comput..

Comprehensive technique for designing and synthesizing TSV Fault-tolerant 3D clock trees

Taewhan Kim, Heechun Park, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Synthesis of arithmetic circuits considering layout effects

Taewhan Kim, Junhyung Um, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design

Taewhan Kim, Hwansoo Han, Yoonseo Choi, 2005, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Clock Tree synthesis for TSV-based 3D IC designs

Taewhan Kim, Tak-Yung Kim, 2011, TODE.

Clock buffer and flip-flop co-optimization for reducing peak current noise

Taewhan Kim, Joohan Kim, 2018, 2018 19th International Symposium on Quality Electronic Design (ISQED).

Hotspots Elimination and Temperature Flattening in VLSI Circuits

Taewhan Kim, Benjamin Carrión Schäfer, Taewhan Kim, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Coupling-aware high-level interconnect synthesis [IC layout]

Taewhan Kim, Chun-Gi Lyuh, Ki-Wook Kim, 2004, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Layout-aware synthesis of arithmetic circuits

Taewhan Kim, Junhyung Um, 2002, DAC '02.

Bus optimization for low-power data path synthesis based on network flow method

Taewhan Kim, Sungpack Hong, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Tutorial: Methodology for designing reliable clock networks

Taewhan Kim, 2013, 2013 IEEE International SOC Conference.

An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization

Taewhan Kim, C. L. Liu, Chaeryung Park, 2000, VLSI Design.

Optimal allocation and placement of thermal sensors for reconfigurable systems and its practical extension

Taewhan Kim, Byunghyun Lee, Taewhan Kim, 2008, 2008 Asia and South Pacific Design Automation Conference.

Address code optimization using code scheduling for digital signal processors

Taewhan Kim, Yoonseo Choi, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Address assignment in DSP code generation - an integrated approach

Taewhan Kim, Yoonseo Choi, Yoonseo Choi, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Minimum delay optimization for domino logic circuits---a coupling-aware approach

Sung-Mo Kang, Taewhan Kim, Seong-Ook Jung, 2003, TODE.

Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design

Taewhan Kim, Yoonseo Choi, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An integrated approach to timing-driven synthesis and placement of arithmetic circuits

Taewhan Kim, Keoncheol Shin, 2004 .

A fine-grained timing driven synthesis of arithmetic circuits

Taewhan Kim, Joohan Kim, 2011, 2011 International SoC Design Conference.

An efficient low-power binding algorithm in high-level synthesis

Taewhan Kim, Yoonseo Choi, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization

Taewhan Kim, Deokjin Joo, Hochang Jang, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Synthesizing Asynchronous Circuits toward Practical Use

Taewhan Kim, Heechun Park, 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing Constraint

Taewhan Kim, Sanghoon Kwak, YongHwan Kim, 2012, TODE.

Scheduling and allocation problems in high-level synthesis

Taewhan Kim, 1993 .

Code compression combined with low-power encoding

Taewhan Kim, Byoungho Lee, 2005, 48th Midwest Symposium on Circuits and Systems, 2005..

Integration of Code Scheduling, Memory Allocation, and Array Binding for Memory-Access Optimization

Taewhan Kim, Jungeun Kim, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis

Taewhan Kim, C. L. Liu, Junhyung Um, 2000, DAC.

Allocation of multi-bit flip-flops in logic synthesis for power optimization

Taewhan Kim, Dongyoun Yi, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Improvement to the Leakage Power Minimization Techniques for Arithmetic Circuits

Taewhan Kim, Daegun Won, 2005 .

Design Rule Evaluation Framework Using Automatic Cell Layout Generator for Design Technology Co-Optimization

Taewhan Kim, Taejoong Song, Kyu-Myung Choi, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Boundary optimization of buffered clock trees for low power

Taewhan Kim, Joohan Kim, 2017, Integr..

Fast allocation of post-silicon tunable buffers to mitigate timing variation

Taewhan Kim, Hyungjung Seo, Jeongwoo Heo, 2014, 2014 International SoC Design Conference (ISOCC).

An integrated algorithm for memory allocation and assignment in high-level synthesis

Taewhan Kim, Preeti Ranjan Panda, Jaewon Seo, 2002, DAC '02.

A Complete Model for Glitch Analysis in Logic Circuits

Taewhan Kim, C. L. Liu, Ki-Seok Chung, 2002, J. Circuits Syst. Comput..

Power-gating-aware high-level synthesis

Taewhan Kim, Eunjoo Choi, Youngsoo Shin, 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

Analysis of Process Variation Effect on Clock Networks

Taewhan Kim, Minseok Kang, 2011 .

A fine-grained technique of NBTI-aware voltage scaling and body biasing for standard cell based designs

Taewhan Kim, Yongho Lee, Taewhan Kim, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Address code generation utilizing memory sharing in DSP processors

Taewhan Kim, Shin Hong, Taewhan Kim, 2005, 48th Midwest Symposium on Circuits and Systems, 2005..

Clock tree embedding for 3D ICs

Taewhan Kim, Tak-Yung Kim, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Comprehensive Analysis and Control of Design Parameters for Power Gated Circuits

Taewhan Kim, Deog-Kyoon Jeong, Yongho Lee, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.