Kenji Anami

发表

Variable bit organization as a new test function for standard memories

Tomohisa Wada, M. Eino, M. Ukita, 1991 .

Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh

Hans Jürgen Mattausch, Kazutami Arimoto, Kazuyasu Fujishima, 2005, IEICE Trans. Electron..

A Smart A/D Converter with tunable resolution and dynamic range for electric power meter

Kenji Anami, Kakeru Kimura, Yoshimi Iso, 2011, 2011 IEEE International Conference on Consumer Electronics (ICCE).

A macro analysis of soft errors in static RAMs

S. Kayano, Kenji Anami, Toru Shiomi, 1988 .

wCloud: “Workshop Cloud” Computing System for Enabling Automotive Control Design in a Collaborative Way

Kazuaki Murakami, Kenji Anami, Takayuki Kando, 2013 .

New bit line architecture for ultra high speed SRAMs-T-shaped bit line and its real application to 256 k BiCMOS TTL SRAM

H. Honda, Tomohisa Wada, Kenji Anami, 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

A 21-mW 4-Mb CMOS SRAM for battery operation

M. Ukita, Kenji Anami, O. Sakamoto, 1991 .

Soft-Error Analysis of Fully Static MOS RAM

Masahiko Yoshimoto, Masahiko Yoshimoto, Kenji Anami, 1982 .

An arrangement for repairing a defective bit in a semiconductor memory device and method for repairing

Tomohisa Wada, Kenji Anami, Shuji Murakami, 1990 .

A 5.8-ns 256-Kb BiCMOS TTL SRAM with T-Shaped bit line architecture

H. Honda, Kenji Anami, Toru Shiomi, 1993 .

A double-word-line structure in bipolar ECL random access memory

S. Kayano, Kenji Anami, Toru Shiomi, 1987 .

A 14-ns 1-Mbit CMOS SRAM with variable bit organization

S. Kayano, Kenji Anami, T. Matsukawa, 1988 .

A 7 ns 1 Mb BiCMOS ECL SRAM with shift redundancy

S. Takano, S. Kayano, H. Honda, 1991 .

New decoding architecture to reduce peak current and its implementation to 4 M ECL SRAM

Kenji Anami, Yoshio Kohno, Atsushi Ohba, 1992, 1992 Symposium on VLSI Circuits Digest of Technical Papers.

Semiconductor memory device with a split word line structure

Kenji Anami, Shuji Murakami, Koreaki Fujita, 1991 .

Soft Error Analysis of Fully Static MOS RAM : A-2: LSI-1

Masahiko Yoshimoto, Kenji Anami, Tsutomu Yoshihara, 1983 .

Simple noise model and low-noise data-output buffer for ultrahigh-speed memories

M. Eino, Kenji Anami, T. Wada, 1990 .

A single-bit-line cross-point cell activation (SCPA) architecture for ultra-low-power SRAM's

M. Ukita, Kenji Anami, Tadato Yamagata, 1993 .

Analog design optimization methodology for ultralow-power circuits using intuitive inversion-level and saturation-level parameters

Kazuaki Murakami, Kenji Anami, Tetsuya Hasebe, 2014 .

Improvement of soft-error rate in MOS SRAMs

S. Kayano, Kenji Anami, K. Ichinose, 1989 .