Ronald G. Dreslinski

发表

An Energy Efficient Parallel Architecture Using Near Threshold Operation

David Blaauw, Ronald G. Dreslinski, Bo Zhai, 2007, 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007).

A low power software-defined-radio baseband processor for the Internet of Things

David Blaauw, Ronald G. Dreslinski, Trevor N. Mudge, 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).

DjiNN and Tonic: DNN as a service and its implications for future warehouse scale computers

Quan Chen, Ronald G. Dreslinski, Trevor N. Mudge, 2015, 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA).

Energy efficient near-threshold chip multi-processing

David Blaauw, Ronald G. Dreslinski, Bo Zhai, 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

A load balancing technique for memory channels

Ronald G. Dreslinski, Trevor N. Mudge, Nam Sung Kim, 2018, MEMSYS.

Lazy cache invalidation for self-modifying codes

Ronald G. Dreslinski, Trevor N. Mudge, Anthony Gutierrez, 2012, CASES '12.

VIX: Virtual Input Crossbar for efficient switch allocation

David Blaauw, Reetuparna Das, Ronald G. Dreslinski, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

3DTUBE: A Design Framework for High-Variation Carbon Nanotube-based Transistor Technology

Ronald G. Dreslinski, Jielun Tan, Aporva Amarnath, 2019, 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores

David Blaauw, Ronald G. Dreslinski, Sudhir Satpathy, 2012, 2012 IEEE International Solid-State Circuits Conference.

3.7 A 1920×1080 30fps 2.3TOPS/W stereo-depth processor for robust autonomous navigation

David Blaauw, Ronald G. Dreslinski, Dennis Sylvester, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

Reining in Long Tails in Warehouse-Scale Computers with Quick Voltage Boosting Using Adrenaline

Ronald G. Dreslinski, Thomas F. Wenisch, Lingjia Tang, 2017, ACM Trans. Comput. Syst..

Architecting an LTE base station with graphics processing units

Scott A. Mahlke, Ronald G. Dreslinski, Chaitali Chakrabarti, 2013, SiPS 2013 Proceedings.

High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service

David Blaauw, Reetuparna Das, Ronald G. Dreslinski, 2012, DAC Design Automation Conference 2012.

Assessing the performance limits of parallelized near-threshold computing

David Blaauw, Ronald G. Dreslinski, Trevor N. Mudge, 2012, DAC Design Automation Conference 2012.

PicoServer Revisited: On the Profitability of Eliminating Intermediate Cache Levels

Trevor Mudge, Ronald G. Dreslinski, Thomas F. Wenisch, 2012 .

A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm

Trevor Mudge, David Blaauw, Ronald G. Dreslinski, 2019, 2019 Symposium on VLSI Circuits.

Optimal and Error-Free Multi-Valued Byzantine Consensus Through Parallel Execution

Ronald G. Dreslinski, Baris Kasikci, Andrew D. Loveless, 2020, IACR Cryptol. ePrint Arch..

Low power interconnects for SIMD computers

David Blaauw, Ronald G. Dreslinski, Sudhir Satpathy, 2011, 2011 Design, Automation & Test in Europe.

A study of Thread Level Parallelism on mobile devices

Krisztián Flautner, Ronald G. Dreslinski, Trevor N. Mudge, 2014, 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

Classifying Ego-Vehicle Road Maneuvers from Dashcam Video

Ronald G. Dreslinski, Thomas F. Wenisch, Stephen A. Zekany, 2019, 2019 IEEE Intelligent Transportation Systems Conference (ITSC).

Sirius Implications for Future Warehouse-Scale Computers

Ronald G. Dreslinski, Trevor N. Mudge, Cheng Li, 2016, IEEE Micro.

Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor With Synthesizable PLL

Christopher Torng, Khalid Al-Hawaj, Christopher Batten, 2019, IEEE Solid-State Circuits Letters.

PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor

Krisztián Flautner, Ronald G. Dreslinski, Trevor N. Mudge, 2006, ASPLOS XII.

Near-threshold computing in FinFET technologies: Opportunities for improved voltage scalability

David Blaauw, Ronald G. Dreslinski, Trevor N. Mudge, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

A hybrid approach to offloading mobile image classification

Ronald G. Dreslinski, Chaitali Chakrabarti, Trevor N. Mudge, 2014, 2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

Composite Cores: Pushing Heterogeneity Into a Core

Scott A. Mahlke, Reetuparna Das, Ronald G. Dreslinski, 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

Diet SODA: A power-efficient processor for digital cameras

Scott A. Mahlke, Ronald G. Dreslinski, Chaitali Chakrabarti, 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

Sources of error in full-system simulation

Ronald G. Dreslinski, Mitchell Hayenga, Trevor N. Mudge, 2014, 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits

David Blaauw, Ronald G. Dreslinski, Trevor N. Mudge, 2010, Proceedings of the IEEE.

Centip3De: A 64-core, 3D stacked, near-threshold system

Trevor Mudge, David Blaauw, Ronald G. Dreslinski, 2012 .

Evolution of thread-level parallelism in desktop applications

Krisztián Flautner, Ronald G. Dreslinski, Trevor N. Mudge, 2010, ISCA.

Circuit design advances for ultra-low power sensing platforms

Trevor Mudge, David Blaauw, Ronald G. Dreslinski, 2010, Defense + Commercial Sensing.

Exploring Fine-Grained Heterogeneity with Composite Cores

Scott A. Mahlke, Reetuparna Das, Ronald G. Dreslinski, 2016, IEEE Transactions on Computers.

A 1920 × 1080 30-frames/s 2.3 TOPS/W Stereo-Depth Processor for Energy-Efficient Autonomous Navigation of Micro Aerial Vehicles

David Blaauw, Ronald G. Dreslinski, Dennis Sylvester, 2018, IEEE J. Solid State Circuits.

Reconfigurable Multicore Server Processors for Low Power Operation

David Blaauw, Ronald G. Dreslinski, Trevor N. Mudge, 2009, SAMOS.

Performance Characterization of Lattice-Based Cryptography Workloads

Ronald G. Dreslinski, Deepika Natarajan, 2020, 2020 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

Checkpointing Exascale Memory Systems with Existing Memory Technologies

Ronald G. Dreslinski, Chaitali Chakrabarti, Trevor N. Mudge, 2016, MEMSYS.

A 4.5Tb/s 3.4Tb/s/W 64×64 switch fabric with self-updating least-recently-granted priority and quality-of-service arbitration in 45nm CMOS

David Blaauw, Ronald G. Dreslinski, Sudhir Satpathy, 2012, 2012 IEEE International Solid-State Circuits Conference.

Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor

Krisztián Flautner, Ronald G. Dreslinski, Trevor N. Mudge, 2008, SAMOS.

Bloom Filter Guided Transaction Scheduling

Ronald G. Dreslinski, Trevor N. Mudge, Geoffrey Blake, 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix–Matrix Multiplication Accelerator

Trevor Mudge, David Blaauw, Ronald G. Dreslinski, 2020, IEEE Journal of Solid-State Circuits.

R2D3: A Reliability Engine for 3D Parallel Systems

Ronald G. Dreslinski, Jielun Tan, Aporva Amarnath, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

Adrenaline: Pinpointing and reining in tail queries with quick voltage boosting

Ronald G. Dreslinski, Thomas F. Wenisch, Lingjia Tang, 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).

Sirius: An Open End-to-End Voice and Vision Personal Assistant and Its Implications for Future Warehouse Scale Computers

Ronald G. Dreslinski, Trevor N. Mudge, Cheng Li, 2015, ASPLOS.

Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS

David Blaauw, Ronald G. Dreslinski, Sudhir Satpathy, 2013, IEEE Journal of Solid-State Circuits.

Full-system analysis and characterization of interactive smartphone applications

Ronald G. Dreslinski, Thomas F. Wenisch, Trevor N. Mudge, 2011, 2011 IEEE International Symposium on Workload Characterization (IISWC).

Using Graphics Processing Units in an LTE Base Station

Hyunseok Lee, Scott A. Mahlke, Ronald G. Dreslinski, 2015, J. Signal Process. Syst..

HETSIM: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework

Trevor Mudge, Ronald G. Dreslinski, Murray Cole, 2020, 2020 IEEE International Symposium on Workload Characterization (IISWC).

Parallelism Analysis of Prominent Desktop Applications: An 18- Year Perspective

Ronald G. Dreslinski, Siying Feng, Yichen Yang, 2019, 2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

14.7 A 288µW programmable deep-learning processor with 270KB on-chip weight storage using non-uniform memory hierarchy for mobile intelligence

David Blaauw, Ronald G. Dreslinski, Trevor N. Mudge, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS

Christopher Torng, Khalid Al-Hawaj, Christopher Batten, 2019, 2019 Symposium on VLSI Circuits.

The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips

Christopher Torng, Christopher Batten, Ronald G. Dreslinski, 2018, IEEE Micro.

Heterogeneous microarchitectures trump voltage scaling for low-power cores

Scott A. Mahlke, Reetuparna Das, Ronald G. Dreslinski, 2014, 2014 23rd International Conference on Parallel Architecture and Compilation (PACT).

Process variation in near-threshold wide SIMD architectures

David Blaauw, Scott A. Mahlke, Ronald G. Dreslinski, 2012, DAC Design Automation Conference 2012.

WarpPool: Sharing requests with inter-warp coalescing for throughput processors

Scott A. Mahlke, Ronald G. Dreslinski, Trevor N. Mudge, 2015, 2015 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

The M5 Simulator: Modeling Networked Systems

Ronald G. Dreslinski, Kevin T. Lim, Ali G. Saidi, 2006, IEEE Micro.

Swizzle-Switch Networks for Many-Core Systems

David Blaauw, Reetuparna Das, Ronald G. Dreslinski, 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Analysis of hardware prefetching across virtual page boundaries

Ronald G. Dreslinski, Trevor N. Mudge, Ali G. Saidi, 2007, CF '07.

A carbon nanotube transistor based RISC-V processor using pass transistor logic

Ronald G. Dreslinski, Siying Feng, Austin Rovinski, 2017, 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Hi-Rise: A High-Radix Switch for 3D Integration with Single-Cycle Arbitration

David Blaauw, Reetuparna Das, Ronald G. Dreslinski, 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.

Integrated 3D-stacked server designs for increasing physical density of key-value stores

Ronald G. Dreslinski, Trevor N. Mudge, Luis Ceze, 2014, ASPLOS.

Analyzing NIC Overheads in Network-Intensive Workloads

Ronald G. Dreslinski, Ali G. Saidi, Steven K. Reinhardt, 2005 .

MBus: An ultra-low power interconnect bus for next generation nanopower systems

David Blaauw, Ronald G. Dreslinski, Zhiyoong Foo, 2015, 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA).

Evaluating private vs. shared last-level caches for energy efficiency in asymmetric multi-cores

Ronald G. Dreslinski, Trevor N. Mudge, Anthony Gutierrez, 2014, 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV).

Designing Future Warehouse-Scale Computers for Sirius, an End-to-End Voice and Vision Personal Assistant

Ronald G. Dreslinski, Trevor N. Mudge, Cheng Li, 2016, TOCS.

XPoint cache: Scaling existing bus-based coherence protocols for 2D and 3D many-core systems

David Blaauw, Reetuparna Das, Ronald G. Dreslinski, 2012, 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT).

MBus: A System Integration Bus for the Modular Microscale Computing Class

David Blaauw, Ronald G. Dreslinski, Zhiyoong Foo, 2016, IEEE Micro.

Reconfigurable energy efficient near threshold cache architectures

David Blaauw, Krisztián Flautner, Ronald G. Dreslinski, 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator

David Blaauw, Ronald G. Dreslinski, Chaitali Chakrabarti, 2018, 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Energy-Autonomous Wireless Communication for Millimeter-Scale Internet-of-Things Sensor Nodes

David Blaauw, Ronald G. Dreslinski, David D. Wentzloff, 2016, IEEE Journal on Selected Areas in Communications.

Accelerating Linear Algebra Kernels on a Massively Parallel Reconfigurable Architecture

Trevor Mudge, David Blaauw, Ronald G. Dreslinski, 2020, ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

Enhancing DRAM Self-Refresh for Idle Power Reduction

Ronald G. Dreslinski, Trevor N. Mudge, Byoungchan Oh, 2016, ISLPED.

TETRIS: A Streaming Accelerator for Physics-Limited 3D Plane-Wave UItrasound Imaging

Ronald G. Dreslinski, Chaitali Chakrabarti, Thomas F. Wenisch, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Centip3De: a many-core prototype exploring 3D integration and near-threshold computing

David Blaauw, Ronald G. Dreslinski, Sudhir Satpathy, 2013, CACM.

Centip3De: A 64-Core, 3D Stacked Near-Threshold System

David Blaauw, Ronald G. Dreslinski, Sudhir Satpathy, 2012, IEEE Micro.

Scaling towards kilo-core processors with asymmetric high-radix topologies

David Blaauw, Reetuparna Das, Ronald G. Dreslinski, 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

A study of mobile device utilization

Carole-Jean Wu, Ronald G. Dreslinski, Trevor N. Mudge, 2015, 2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

Parallelization techniques for implementing trellis algorithms on graphics processors

Scott A. Mahlke, Ronald G. Dreslinski, Chaitali Chakrabarti, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

Exploring DRAM organizations for energy-efficient and resilient exascale memories

David Blaauw, Ronald G. Dreslinski, Chaitali Chakrabarti, 2013, 2013 SC - International Conference for High Performance Computing, Networking, Storage and Analysis (SC).

1 A 2 . 9 TOPS / W Deep Convolutional Neural Network SoC in FD-SOI 28 nm for Intelligent Embedded Systems

Trevor Mudge, Ronald G. Dreslinski, Dennis Sylvester, 2017 .

Embedded way prediction for last-level caches

Ronald G. Dreslinski, Thomas F. Wenisch, Faissal M. Sleiman, 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).

SMART: STT-MRAM architecture for smart activation and sensing

Ronald G. Dreslinski, Trevor N. Mudge, Nam Sung Kim, 2019, MEMSYS.

The Performance Potential of an Integrated Network Interface

Ronald G. Dreslinski, Steven K. Reinhardt, Nathan L. Binkert, 2004 .

Fully-Autonomous SoC Synthesis using Customizable Cell-Based Synthesizable Analog Circuits

David Blaauw, Ronald G. Dreslinski, David D. Wentzloff, 2019 .

WiBench: An open source kernel suite for benchmarking wireless systems

Scott A. Mahlke, Ronald G. Dreslinski, Chaitali Chakrabarti, 2013, 2013 IEEE International Symposium on Workload Characterization (IISWC).

Proactive transaction scheduling for contention management

Ronald G. Dreslinski, Trevor N. Mudge, Geoffrey Blake, 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Hardware acceleration for similarity measurement in natural language processing

Ronald G. Dreslinski, Thomas F. Wenisch, Jichuan Chang, 2013, International Symposium on Low Power Electronics and Design (ISLPED).

Performance analysis of system overheads in TCP/IP workloads

Ronald G. Dreslinski, Ali G. Saidi, Steven K. Reinhardt, 2005, 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05).

Quality-of-service for a high-radix switch

David Blaauw, Reetuparna Das, Ronald G. Dreslinski, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

Limits of Parallelism and Boosting in Dim Silicon

David Blaauw, Ronald G. Dreslinski, Trevor N. Mudge, 2013, IEEE Micro.

Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm

David Blaauw, Ronald G. Dreslinski, Chaitali Chakrabarti, 2021, 2021 Symposium on VLSI Circuits.

RISC-V Reward: Building Out-of-Order Processors in a Computer Architecture Design Course with an Open-Source ISA

Ronald G. Dreslinski, Jielun Tan, Stephen A. Zekany, 2021, SIGCSE.

A Survey Describing Beyond Si Transistors and Exploring Their Implications for Future Processors

Ronald G. Dreslinski, Aporva Amarnath, Javad Bagherzadeh, 2021, ACM J. Emerg. Technol. Comput. Syst..

A Holistic Solution for Reliability of 3D Parallel Systems

Ronald G. Dreslinski, Jielun Tan, Aporva Amarnath, 2022, ACM J. Emerg. Technol. Comput. Syst..

SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator

Ronald G. Dreslinski, Michael F. P. O'Boyle, Aporva Amarnath, 2021, MICRO.

A Deep Dive Into Understanding The Random Walk-Based Temporal Graph Learning

Ronald G. Dreslinski, Danai Koutra, Trevor N. Mudge, 2021, 2021 IEEE International Symposium on Workload Characterization (IISWC).

CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics

Ronald G. Dreslinski, Chaitali Chakrabarti, Michael F. P. O'Boyle, 2021, 2021 58th ACM/IEEE Design Automation Conference (DAC).

CHEX-MIX: Combining Homomorphic Encryption with Trusted Execution Environments for Two-party Oblivious Inference in the Cloud

Ronald G. Dreslinski, Deepika Natarajan, Wei Dai, 2021, IACR Cryptol. ePrint Arch..

Improving Performance of Flash Based Key-Value Stores Using Storage Class Memory as a Volatile Memory Extension

Ronald G. Dreslinski, Vaibhav Gogte, Jason B. Akers, 2021, USENIX Annual Technical Conference.

Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads Using Hardware-Software Co-Design

Scott A. Mahlke, Ronald G. Dreslinski, Michael F. P. O'Boyle, 2021, 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA).

Reevaluating Fast Dual-Voltage Power Rail Switching Circuitry

Trevor Mudge, David Blaauw, Ronald G. Dreslinski, 2012 .

Sirius: An Open End-to-End Voice and Vision Personal Assistant and Its Implications for Future Warehouse Scale Computers

Ronald G. Dreslinski, Trevor N. Mudge, Austin Rovinski, 2015, ASPLOS.