Y. Kohyama

A latch-up-like new failure mechanism for high-density CMOS dynamic RAMs

T. Furuyama, H. Ishiuchi, Kenji Natori, 1990 .

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

G. Burbach, D. Greenlaw, S.F. Huang, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Suppression of crosstalk by using backside deep trench isolation for 1.12μm backside illuminated CMOS image sensor

Y. Kohyama, H. Aikawa, Y. Takegawa, 2012, 2012 International Electron Devices Meeting.

Level-specific strategy of KrF microlithography for 130 nm DRAMs

T. Sutani, K. Tsuchida, Y. Kohyama, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Body voltage and history effect sensitivity to key device parameters in 90 nm PD-SOI

M. Sherony, S. Narasimha, Y. Kohyama, 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

Integration technology of polymetal (W/WSiN/Poly-Si) dual gate CMOS for 1 Gbit DRAMs and beyond

Y. Akasaka, Y. Toyoshima, K. Nakajima, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

High performance CMOS devices on SOI for 90 nm technology enhanced by RSD (raised source/drain) and thermal cycle/spacer engineering

D. Mocuta, Y. Toyoshima, B.H. Lee, 2003, IEEE International Electron Devices Meeting 2003.