Jouke Verbree

On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking

Erik Jan Marinissen, Philippe Roussel, Dimitrios Velenis, 2010, 2010 15th IEEE European Test Symposium.

A structured and scalable test access architecture for TSV-based 3D stacked ICs

Mario H. Konijnenburg, Erik Jan Marinissen, Jouke Verbree, 2010, 2010 28th VLSI Test Symposium (VTS).

A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

Mario H. Konijnenburg, Erik Jan Marinissen, Chun-Chuan Chi, 2012, J. Electron. Test..

Test-architecture optimization for TSV-based 3D stacked ICs

Erik Jan Marinissen, Krishnendu Chakrabarty, Sandeep Kumar Goel, 2010, 2010 15th IEEE European Test Symposium.

Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs

Erik Jan Marinissen, Krishnendu Chakrabarty, Sandeep Kumar Goel, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

3D DfT architecture for pre-bond and post-bond testing

Mario H. Konijnenburg, Erik Jan Marinissen, Chun-Chuan Chi, 2010, 2010 IEEE International 3D Systems Integration Conference (3DIC).

Junction Optimization for Embedded 40nm FN/FN Flash Memory

Jouke Verbree, Yi Ning Chen, Alessandro Baiano, 2015, 2015 IEEE International Memory Workshop (IMW).

On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICs

Erik Jan Marinissen, Said Hamdioui, Mottaqiallah Taouil, 2010, 2010 IEEE International Test Conference.

3D design‐for‐test architecture

Mario Konijnenburg, Vivek Chickermane, Erik Jan Marinissen, 2019 .