Vijay Narayanan

High-mobility high-Ge-content Si1−xGex-OI PMOS FinFETs with fins formed using 3D germanium condensation with Ge fraction up to x∼ 0.7, scaled EOT∼8.5Å and ∼10nm fin width

E. Leobandung, P. Hashemi, Takashi Ando, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

Characterizing the soft error vulnerability of multicores running multithreaded applications

Anand Sivasubramaniam, Niranjan Soundararajan, Vijay Narayanan, 2010, SIGMETRICS '10.

Electron mobility in thin In0.53Ga0.47As channel

X. Sun, C.-C. Yeh, Martin M. Frank, 2017, 2017 47th European Solid-State Device Research Conference (ESSDERC).

Advanced high-k dielectric stacks with polySi and metal gates: Recent progress and current challenges

Martin M. Frank, Vijay Narayanan, Evgeni P. Gusev, 2006, IBM J. Res. Dev..

A Quantitative Evaluation Framework for Missing Value Imputation Algorithms pdf

Johannes Gehrke, Vinod Nair, S. Sathiya Keerthi, 2013, ArXiv.

Interface engineering of Si1−xGex gate stacks for high performance dual channel CMOS

Hemanth Jagannathan, Takashi Ando, Vijay Narayanan, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

PBTI in InGaAs MOS capacitors with Al2O3/HfO2/TiN gate stacks: Interface-state generation

Martin M. Frank, Takashi Ando, Vijay Narayanan, 2018, 2018 IEEE International Reliability Physics Symposium (IRPS).

Robust Coreset Construction for Distributed Machine Learning

Ting He, Kevin S. Chan, Shiqiang Wang, 2019, 2019 IEEE Global Communications Conference (GLOBECOM).