Yusuke Yamada

A 3-Dimensional Wafer-Level Stacking Technology with Precise Vertical Interconnections to MEMS Applications

K. W. Lee, M. Koyanagi, H. Kurino, 2001 .

A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors

Masayuki Nakajima, Takumi Okamoto, Koichi Yamaguchi, 2009, IEEE Journal of Solid-State Circuits.

A chip-stacked memory for on-chip SRAM-rich SoCs and processors

Masayuki Nakajima, Takumi Okamoto, Koichi Yamaguchi, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

New Three-Dimensional Integration Technology Using Chip-to-Wafer Bonding to Achieve Ultimate Super-Chip Integration

Mitsumasa Koyanagi, Takafumi Fukushima, M. Koyanagi, 2005 .

System in wafer-level package technology with RDL-first process

Tomohiro Nishiyama, Masaya Kawano, Kazuyuki Mineo, 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

Three-dimensional shared memory fabricated using wafer stacking technology

K. W. Lee, T. Ono, Tomokatsu Mizukusa, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).