Masato Sumiyoshi

Design and evaluation of the cache coherent multistage interconnection network with temporary directory

Hideharu Amano, Takashi Midorikawa, Yasuki Tanabe, 2006 .

A VLIW Vector Media Coprocessor With Cascaded SIMD ALUs

Masaki Nakagawa, Shunichi Ishiwata, Takashi Miyamori, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications

Takashi Miyamori, Yasuki Tanabe, Manabu Nishiyama, 2012, 2012 IEEE International Solid-State Circuits Conference.

Design and Evaluation of a Switch Architecture for Multistage Interconnection Network with Temporary Directory

Hideharu Amano, Takashi Midorikawa, Yasuki Tanabe, 2004, ISCA PDCS.