P. Poechmueller

Fault-tolerant designs for 256 Mb DRAM

John K. DeBrosse, Toshiaki Kirihata, Matthew R. Wordeman, 1995, Digest of Technical Papers., Symposium on VLSI Circuits..

On the retention time distribution of dual-channel vertical DRAM technologies

D. Casarotto, P. Poechmueller, J. Beintner, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

Multilevel simulation tool for designing fault-tolerant VLSI array processors

G. K. Sharma, M. Glesner, P. Poechmueller, 1991, [1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design.

A 286 mm/sup 2/ 256 Mb DRAM with X32 both-ends DQ

P. Poechmueller, M. Yoshida, J. DeBrosse, 1995, Digest of Technical Papers., Symposium on VLSI Circuits..

Design methodology for systematic derivation of fault-tolerant processor array architectures

Dimitrios Soudris, Constantinos E. Goutis, E. D. Kyriakis-Bitzaros, 1998 .

Design methodology for systematic derivation of fault-tolerant array processors

M. Glesner, P. Poechmueller, E.D. Kyriakis-Bitzaros, 1992, CompEuro 1992 Proceedings Computer Systems and Software Engineering.

A new approach for multilevel logic cell optimization

M. Glesner, P. Poechmueller, 1991, [1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design.