K. N. Vijeyakumar

发表

Implementation of Protection Techniques against Single Event upsets for IIR Filters

R. Selvanathan, K. N. Vijeyakumar, 2011 .

Design of High Speed Serial-Serial Multiplier for OFDM Applications

N. Saravanakumar, A. Nirmal Kumar, K. N. Vijeyakumar, 2013 .

Removal of High density impulse noise using Morphological based adaptive unsymmetrical trimmed mid-Point filter

A. Ebenezer Jeyakumar, K. N. Vijeyakumar, S. Saravanakumar, 2014, J. Comput. Sci..

Target Tracking in Sensor Networks Using Energy Efficient Prediction Based Clustering Algorithm

K. N. Vijeyakumar, V. Pravina Dayan, 2012 .

Design of Low Power Full Adder Using Active Level Driving Circuit

V. Sumathy, K. N. Vijeyakumar, M. Nithya, 2012 .

Design and Performance Estimation of Efficient Approximate Carry Select Adder

P. Poongodi, K. N. Vijeyakumar, V. S. Nishok, 2018 .

Design of Low- Power High-Speed Error Tolerant Shift and Add Multiplier

V. Sumathy, K. N. Vijeyakumar, C. Chrisjin Gnana Suji, 2011 .

FPGA based implementation of MPPT algorithms for photovoltaic system under partial shading conditions

B. Vinoth Kumar, Vijeyakumar Krishnasamy Natarajan, K. N. Vijeyakumar, 2020, Microprocess. Microsystems.

Design and Implementation of Reduced Power Energy Efficient Binary Coded Decimal Adder

N. Saravanakumar, S. Saranya, K. N. Vijeyakumar, 2019 .

A Novel n-Decimal Reversible Radix Binary-Coded Decimal Multiplier Using Radix Encoding Scheme

K. Saranya, K. N. Vijeyakumar, Saranya Karunamurthi, 2020, Circuits Syst. Signal Process..

VLSI Implementation of High Speed Energy-Efficient Truncated Multiplier

S. Elango, Kalaiselvi Sundaram, K. N. Vijeyakumar, 2018, J. Circuits Syst. Comput..

FPGA Implementation of Low Power Hardware Efficient Flagged Binary Coded Decimal Adder

V. Sumathy, S. Elango, S. Saravanakumar, 2012 .

VLSI Implementation of Area-Efficient Truncated Modified Booth Multiplier for Signal Processing Applications

V. Sumathy, S. Elango, K. N. Vijeyakumar, 2014 .

Three-phase to K-phase power conversion using voltage fed quasi Z source direct matrix converter with maximum constant boost control technique

K. N. Vijeyakumar, N. Saravanakumar, S. Manivannan, 2022, Electrical Engineering.

Three-phase power conversion using quasi Z source direct matrix converter (QZSDMC) for fixed frequency to variable frequency using direct duty ratio based pulse width modulation technique

K. N. Vijeyakumar, S. Manivannan, N. Saravanakumar, 2021 .

Design Of Hardware Efficient High Speed Multiplier Using Modified Ternary Logic

K. N. Vijeyakumar, S. Tamilselvan, V. Sumathy, 2012 .

VLSI Implementation of Area-Efficient Truncated Modified Booth Multiplier for Signal Processing Applications

K. N. Vijeyakumar, V. Sumathy, S. Elango, 2014, Arabian Journal for Science and Engineering.

A Novel n-Decimal Reversible Radix Binary-Coded Decimal Multiplier Using Radix Encoding Scheme

K. N. Vijeyakumar, K. Saranya, 2020, Circuits, Systems, and Signal Processing.