A. Mercha

发表

A 1 V 23 GHz Low-Noise Amplifier in 45 nm Planar Bulk-CMOS Technology With High-$Q$ Above-IC Inductors

Chung-Yu Wu, Wen-Chieh Wang, Zue-Der Huang, 2009, IEEE Microwave and Wireless Components Letters.

Impact of multi-gate device architectures on digital and analog circuits and its implications on System-On-Chip technologies

P. Wambacq, A. Mercha, G. Van der Plas, 2013, 2013 IEEE International Electron Devices Meeting.

Low-power voltage-controlled oscillators in 90-nm CMOS using high-quality thin-film postprocessed inductors

P. Wambacq, G. Carchon, A. Mercha, 2005, IEEE Journal of Solid-State Circuits.

Class 3 HBM and class M4 MM ESD protected 5.5 GHz LNA in 90 nm RFCMOS using above-IC inductor

P. Soussan, P. Wambacq, G. Groeseneken, 2005, 2005 Electrical Overstress/Electrostatic Discharge Symposium.

Vertical device architecture for 5nm and beyond: Device & circuit implications

P. Wambacq, A. Mercha, J. Ryckaert, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Reliability study in capacitor less 1T-RAM cells on SOI

A. Mercha, E. Simoen, N. Collaert, 2010, 2010 IEEE International SOI Conference (SOI).

Variability and technology aware SRAM Product yield maximization

A. Mercha, P. Roussel, D. Verkest, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

PSP-based compact FinFET model describing dc and RF measurements

G. Gildenblat, G.D.J. Smit, D.B.M. Klaassen, 2006, 2006 International Electron Devices Meeting.

Hot-carrier degradation on the analogue/RF performances of a 90nm RF-CMOS technology demonstrated in a 900MHz low-power LNA

P. Wambacq, A. Mercha, S. Decoutere, 2005, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..

Group IV channels for 7nm FinFETs: Performance for SoCs power and speed metrics

A. Mercha, D. Verkest, P. Raghavan, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Device and circuit-level analog performance trade-offs: a comparative study of planar bulk FETs versus FinFETs

P. Wambacq, B. Parvais, A. Mercha, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS

P. Wambacq, A. Mercha, S. Decoutere, 2004, IEEE Journal of Solid-State Circuits.

Advanced Process Modules for (sub-) 45nm Analog/RF CMOS - Technology Description and Modeling Challenges

B. Parvais, A. Mercha, S. Decoutere, 2006, 2006 European Microwave Integrated Circuits Conference.

Low-cost feedback-enabled LNAs in 45nm CMOS

P. Wambacq, A. Mercha, J. Borremans, 2009, 2009 Proceedings of ESSCIRC.

What can low-frequency noise learn us about the quality of thin-gate dielectrics?

A. Mercha, E. Simoen, C. Claeys, 2003 .

Perspectives of (sub-) 32nm CMOS for Analog/RF and mm-wave Applications

B. Parvais, G. Groeseneken, W. Sansen, 2008, 2008 European Microwave Integrated Circuit Conference.

Comment on ‘Comparison of excess 1/f noise spectra in trimmed and untrimmed thick film resistors’

A. Mercha, L.K.J. Vandamme, R. Feyaerts, 2001 .

Towards optimally shaped fins in p-channel tri-gate FETs: can fin height be reduced further?

R. Rooyackers, A. Mercha, N. Collaert, 2005, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..

Analysis oftheFinFETparasitics forimproved RFperformances

Willy Sansen, A. Mercha, S. Decoutere, 2007 .

High-Frequency Noise Performance of 60-nm Gate-Length FinFETs

J.-P. Raskin, A. Mercha, S. Decoutere, 2008, IEEE Transactions on Electron Devices.

A 10-Bit current-steering FinFET D/A converter

G. Knoblinger, F. Kuttner, D. Schmitt-Landsiedel, 2008, 2008 IEEE International SOI Conference.

Analysis of the FinFET parasitics for improved RF performances

B. Parvais, A. Mercha, S. Decoutere, 2007, 2007 IEEE International SOI Conference.

Dependence of finFET RF performance on fin width

J.-P. Raskin, A. Mercha, S. Decoutere, 2006, Digest of Papers. 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.

Planar Bulk MOSFETs Versus FinFETs: An Analog/RF Perspective

A. Mercha, S. Decoutere, S. Donnay, 2006, IEEE Transactions on Electron Devices.

Analog design challenges and trade-offs using emerging materials and devices

G. Knoblinger, A. Mercha, B. Parvais, 2007, ESSDERC 2007 - 37th European Solid State Device Research Conference.

Double-Gate finFETs as a CMOS Technology Downscaling Option: An RF Perspective

A. Mercha, B. Parvais, S. Nuttinck, 2007, IEEE Transactions on Electron Devices.

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

P. Soussan, E. Beyne, A. Mercha, 2010, 2010 International Electron Devices Meeting.

Suitability of FinFET technology for low-power mixed-signal applications

P. Wambacq, B. Parvais, R. Rooyackers, 2006, 2006 IEEE International Conference on IC Design and Technology.

Stochastic Matching Properties of FinFETs

B. Parvais, A. Mercha, S. Decoutere, 2006, IEEE Electron Device Letters.

An integrated 5 GHz low-noise amplifier with 5.5 kV HBM ESD protection in 90 nm RF CMOS

P. Wambacq, A. Mercha, S. Decoutere, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

The device architecture dilemma for CMOS technologies: Opportunities & challenges of finFET over planar MOSFET

B. Parvais, R. Rooyackers, A. Mercha, 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

Impact of Stochastic Mismatch on Measured SRAM Performance of FinFETs with Resist/Spacer-Defined Fins: Role of Line-Edge-Roughness

R. Rooyackers, A. Mercha, E. Augendre, 2006, 2006 International Electron Devices Meeting.

90nm RF CMOS technology for low-power 900MHz applications [amplifier example]

P. Wambacq, R. Rooyackers, A. Mercha, 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

Multi-gate devices for the 32nm technology node and beyond

R. Rooyackers, A. Mercha, L. Witters, 2007, ESSDERC 2007 - 37th European Solid State Device Research Conference.

Integration of a 90nm RF CMOS technology (200GHz f/sub max/ - 150GHz f/sub T/ NMOS) demonstrated on a 5GHz LNA

P. Wambacq, A. Mercha, S. Decoutere, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Impact of scaling on analog/RF CMOS performance

P. Wambacq, A. Mercha, S. Decoutere, 2004, Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004..

Analog and RF circuits in 45 nm CMOS and below: planar bulk versus FinFET

B. Parvais, A. Mercha, S. Decoutere, 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

Perspective of RF design in future planar and FinFET CMOS

P. Wambacq, B. Parvais, A. Mercha, 2008, 2008 IEEE Radio Frequency Integrated Circuits Symposium.

A 5-25 GHz high linearity, low-noise CMOS amplifier

H. Jacobsson, A. Mercha, G. Carchon, 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

A low-cost 90nm RF-CMOS platform for record RF circuit performance

P. Soussan, P. Wambacq, A. Mercha, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Self-heating on bulk FinFET from 14nm down to 7nm node

A. Mercha, D. Verkest, P. Raghavan, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

High-mobility 0.85nm-EOT Si0.45Ge0.55-pFETs: Delivering high performance at scaled VDD

A. Mercha, L. Witters, J. Mitard, 2010, 2010 International Electron Devices Meeting.

Low-power 5 GHz LNA and VCO in 90 nm RF CMOS

P. Wambacq, H. Jacobsson, A. Mercha, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

FinFET compact modelling for analogue and RF applications

G.D.J. Smit, D.B.M. Klaassen, A. Mercha, 2010, 2010 International Electron Devices Meeting.

Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance

P. Soussan, E. Beyne, A. Mercha, 2010, 2010 Symposium on VLSI Technology.

Characterization, modeling, and optimization of FinFET MOS varactors

B. Parvais, A. Mercha, S. Decoutere, 2007, 2007 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.

Lateral versus vertical gate-all-around FETs for beyond 7nm technologies

A. Mercha, D. Verkest, N. Collaert, 2014, 72nd Device Research Conference.

Inversion Layer Quantization Impact on the Interpretation of 1/f Noise in Deep Submicron CMOS Transistors

A. Mercha, E. Simoen, C. Claeys, 2002, 32nd European Solid-State Device Research Conference.

Low-frequency noise in low temperature unhydrogenated polysilicon thin film transistors

Olivier Bonnaud, A. Mercha, R. Carin, 2000 .

Experimental assessment of self-heating in SOI FinFETs

G.D.J. Smit, D.B.M. Klaassen, A. Mercha, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Electron valence band tunnelling induced excess Lorentzian noise in fully depleted SOI transistors

A. Mercha, E. Simoen, C. Claeys, 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..

Radiation-Induced Back Channel Leakage in 60 MeV-Proton-Irradiated 0 . 10 μ m-CMOS Partially Depleted SOI MOSFETs

A. Mercha, E. Simoen, C. Claeys, .

Low Phase Noise sub-1 V Supply 12 and 18 GHz VCOs in 90 nm CMOS

H. Jacobsson, A. Mercha, Mingquan Bao, 2006, 2006 IEEE MTT-S International Microwave Symposium Digest.

3D stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective bonding

P. Soussan, E. Beyne, C. Huyghebaert, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

A 20 GHz sub-1V low noise amplifier and a resistive mixer in 90 nm CMOS technology

H. Jacobsson, A. Mercha, G. Carchon, 2005, 2005 Asia-Pacific Microwave Conference Proceedings.

Critical discussion of the front-back gate coupling effect on the low-frequency noise in fully depleted SOI MOSFETs

A. Mercha, E. Simoen, C. Claeys, 2004, IEEE Transactions on Electron Devices.

Low-frequency noise behavior of SiO/sub 2/--HfO/sub 2/ dual-layer gate dielectric nMOSFETs with different interfacial oxide thickness

A. Mercha, L. Pantisano, E. Simoen, 2004, IEEE Transactions on Electron Devices.

Explaining the parameters of the electron valence-band tunneling related Lorentzian noise in fully depleted SOI MOSFETs

A. Mercha, E. Simoen, C. Claeys, 2003, IEEE Electron Device Letters.

Analysis of the activation energy of the subthreshold current in laser- and solid-phase-crystallized polycrystalline silicon thin-film transistors

A. Mercha, Laurent Pichon, A. Mercha, 2000 .

Standard cell level parasitics assessment in 20nm BPL and 14nm BFF

A. Mercha, D. Verkest, M. Badaroglu, 2012, International Electron Devices Meeting.

Layout-induced stress effects in 14nm & 10nm FinFETs and their impact on performance

A. Mercha, G. Van der Plas, D. Verkest, 2013, 2013 Symposium on VLSI Circuits.

Determination and Validation of New Nonlinear FinFET Model Based on Lookup Tables

A. Caddemi, B. Parvais, A. Mercha, 2007, IEEE Microwave and Wireless Components Letters.

Impact of 7.5-MeV proton irradiation on front-back gate coupling effect in ultra thin gate oxide FD-SOI n-MOSFETs

A. Mercha, E. Simoen, C. Claeys, 2004, IEEE Transactions on Nuclear Science.

Low-Frequency Noise Assessment of Silicon Passivated Ge pMOSFETs With TiN/TaN/ $\hbox{HfO}_{2}$ Gate Stack

A. Mercha, B. Kaczer, E. Simoen, 2007, IEEE Electron Device Letters.

Matching Performance of FinFET Devices With Fin Widths Down to 10 nm

A. Mercha, S. Decoutere, N. Collaert, 2009, IEEE Electron Device Letters.

Radiation-induced back channel leakage in 60 MeV-proton-irradiated 0.10 /spl mu/m-CMOS partially depleted SOI MOSFETs

A. Mercha, E. Simoen, C. Claeys, 2003, Proceedings of the 7th European Conference on Radiation and Its Effects on Components and Systems, 2003. RADECS 2003..