Byung-Gook Park

发表

Size efficient low‐noise amplifier for 2.4 GHz ISM‐band transceiver

Hyungcheol Shin, Hee-Sauk Jhon, Hakchul Jung, 2009 .

A Gated Twin-Bit (GTB) Nonvolatile Memory Device and Its Fabrication Method

Hyungcheol Shin, Il Han Park, Byung-Gook Park, 2009, IEEE Transactions on Nanotechnology.

Improving the cell characteristics using arch-active profile in NAND flash memory having 60.nm design rule

Il Han Park, Byung-Gook Park, Jong Duk Lee, 2008 .

New program inhibition scheme for high boosting efficiency in three-dimensional NAND array

Byung-Gook Park, Joo Yun Seo, Yoon Kim, 2014 .

4-bit FinFET SONOS flash memory: Optimization of structure and 3D numerical simulation (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))

Byung-Gook Park, Yoon Young Kim, Jang-Gn Yun, 2007 .

PAPER Special Section on Fundamentals and Applications of Advanced Semiconductor Devices Design and Simulation of Asymmetric MOSFETs

Nonmembers, Woo Young Choi, Byung-Gook Park, 2007 .

Programmable virtual source/drain MOSFETs

Hyungcheol Shin, Il Han Park, Chilhee Chung, 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

A Subthreshold Slope and Low-frequency Noise Characteristics in Charge Trap Flash Memories with Gate-All-Around and Planar Structure

Hyungcheol Shin, Byung-Gook Park, Jong-Ho Lee, 2012 .

8mW 17/24 GHz dual-band CMOS low-noise amplifier for ISM-band application

Hyundong Shin, Hee-Sauk Jhon, Byung-Gook Park, 2008 .

Fabrication Methods for Nanowire Tunnel FET with Locally Concentrated Silicon-germanium Channel

Byung-Gook Park, Kitae Lee, Hyun-Min Kim, 2019, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE.

Comparative study on the energy efficiency of logic gates based on single-electron transistor technology

Byung-Gook Park, Dong Myong Kim, In-Young Chung, 2009 .

A New 1T DRAM Cell: Cone Type 1T DRAM Cell

Byung-Gook Park, Seongjae Cho, Doo-Hyun Kim, 2011, IEICE Trans. Electron..

Overview of Channel-Stacked NAND Flash Memory

Sang-Ho Lee, Byung-Gook Park, Joo Yun Seo, 2015 .

Synaptic device using a floating fin-body MOSFET with memory functionality for neural network

Byung-Gook Park, Jong-Ho Lee, Sung-Tae Lee, 2019 .

Reverse-order source/drain formation with double offset spacer (RODOS) for low-power and high-speed application

Woo Young Choi, Byung-Gook Park, Jong Duk Lee, 2003 .

A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)

Hyungcheol Shin, Byung-Gook Park, Jong-Ho Lee, 2010, SDM.

Improving the cell characteristics using arch-active profile in NAND flash memory having 60.nm design rule

Hyungcheol Shin, Il Han Park, Byung-Gook Park, 2008, 2008 IEEE Silicon Nanoelectronics Workshop.

Design and Fabrication of Asymmetric MOSFETs Using a Novel Self-Aligned Structure

Woo Young Choi, Byung-Gook Park, Jong Duk Lee, 2007, IEEE Transactions on Electron Devices.

Integrate-and-fire neuron circuit and synaptic device with a floating body MOSFET

Byung-Gook Park, Hyungjin Kim, Jong-Ho Lee, 2014, 2014 Silicon Nanoelectronics Workshop (SNW).

A new device characteristic model generation by machine learning

Byung-Gook Park, Min-Hye Oh, Min-Woo Kwon, 2019, 2019 Electron Devices Technology and Manufacturing Conference (EDTM).

Investigation of Frequency Dependent Sensitivity of Noise Figure on Device Parameters in 65 nm CMOS

Hyungcheol Shin, Hee-Sauk Jhon, Hakchul Jung, 2009 .

Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2008, IEICE Trans. Electron..

Design and Simulation of Asymmetric MOSFETs

Woo Young Choi, Byung-Gook Park, Jong Duk Lee, 2006, IEICE Trans. Electron..

Compact Bit-line STacked ARray(STAR)

Byung-Gook Park, Se Hwan Park, Joo Yun Seo, 2011 .

Reverse-order source/drain formation with double offset spacer (RODOS) for CMOS low-power, high-speed and low-noise amplifiers

Woo Young Choi, Byung-Gook Park, Jong Duk Lee, 2003, ISLPED '03.

Investigation of Retention Characteristics Caused by Charge Loss for Charge Trap NAND Flash Memory

Byung-Gook Park, Seongjae Cho, Young-Min Kim, 2017 .

Vertical stack array of one-time programmable nonvolatile memory based on pn-junction diode and its operation scheme for faster access

Byung-Gook Park, Seongjae Cho, Sunghun Jung, 2014, IEICE Electron. Express.

Design and optimization of two-bit double-gate nonvolatile memory cell for highly reliable operation

Il Han Park, Ki-Whan Song, Byung-Gook Park, 2006 .

Compact Neuromorphic System With Four-Terminal Si-Based Synaptic Devices for Spiking Neural Networks

Byung-Gook Park, Hyungjin Kim, Jeong-Jun Lee, 2017, IEEE Transactions on Electron Devices.

Nanoscale SONOS Flash Memories(Session B6 Si-Devices II)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))

Il Han Park, Byung-Gook Park, Dong Gun Park, 2004 .

A Simple compact model for hot carrier injection phenomenon in 32 nm NAND flash memory device

Myounggon Kang, Hyungcheol Shin, Il Han Park, 2010, 2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC).

Low power size‐efficient CMOS UWB low‐noise amplifier design

Hyungcheol Shin, Hee-Sauk Jhon, Jongwook Jeon, 2009 .

Application of Area-Saving RF Test Structure on Mobility Extraction

Byung-Gook Park, Jong Duk Lee, Hyungcheol Shin, 2009 .

Reverse-Order Source/Drain with Double Offset Spacer (RODOS) for Sub-5Onm Low-Power and High-Speed MOSFET Design(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)

Woo Young Choi, Byung-Gook Park, Byung Yong Choi, 2003 .

Three-Dimensional NAND Flash Memory Based on Single-Crystalline Channel Stacked Array

Byung-Gook Park, Se Hwan Park, Yoon Kim, 2013, IEEE Electron Device Letters.

Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2009, IEICE Trans. Electron..

Bias Polarity Dependent Resistive Switching Behaviors in Silicon Nitride-Based Memory Cell

Byung-Gook Park, Seongjae Cho, Min-Hwi Kim, 2016, IEICE Trans. Electron..

Investigation of Feasibility of Tunneling Field Effect Transistor (TFET) as Highly Sensitive and Multi-sensing Biosensors

Byung-Gook Park, Dae Woong Kwon, Sihyun Kim, 2017 .

3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array

Hyungcheol Shin, Yoon Kim, Byung-Gook Park, 2009, IEICE Trans. Electron..

Schottky Barrier Tunnel Field-Effect Transistor using Spacer Technique

Min-Chul Sun, Byung-Gook Park, Hyunwoo Kim, 2014 .

The novel SCR-based ESD protection with low triggering and high holding voltages

Myounggon Kang, Hyungcheol Shin, Ki-Whan Song, 2011, Microelectron. J..

O2-Enhanced surface treatment of Ge epitaxially grown on Si for heterogeneous Ge technology

Byung-Gook Park, Seongjae Cho, James S. Harris, 2014, The 18th IEEE International Symposium on Consumer Electronics (ISCE 2014).

Channel-Stacked NAND Flash Memory With Tied Bit-Line and Ground Select Transistor

Sang-Ho Lee, Byung-Gook Park, Dae Woong Kwon, 2016, IEEE Electron Device Letters.

Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)

Byung-Gook Park, Se Hwan Park, Hyungjin Kim, 2012, IEICE Trans. Electron..

A 2-Bit Recessed Channel Nonvolatile Memory Device With a Lifted Charge-Trapping Node

Il Han Park, Byung-Gook Park, Jong Duk Lee, 2009 .

Reduction of Breakdown Voltage in I-MOS Devices

Woo Young Choi, Byung-Gook Park, Jong Duk Lee, 2006 .

Three-Dimensional nand Flash Architecture Design Based on Single-Crystalline STacked ARray

Myounggon Kang, Hyungcheol Shin, Byung-Gook Park, 2012, IEEE Transactions on Electron Devices.

Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer

Byung-Gook Park, Seongjae Cho, Kwon-Chil Kang, 2010, IEICE Trans. Electron..

Implementation of inhibitory operation in neuromorphic system

Byung-Gook Park, Hyungjin Kim, Jeong-Jun Lee, 2017, 2017 Silicon Nanoelectronics Workshop (SNW).

Investigation into the effect of the variation of gate dimensions on program characteristics in 3D NAND flash array

Hyungcheol Shin, Byung-Gook Park, Yoon Kim, 2012, 2012 IEEE Silicon Nanoelectronics Workshop (SNW).

A Highly Scalable Split-Gate SONOS Flash Memory with Programmable-Pass and Pure-Select Transistors for Sub-90-nm Technology

Chilhee Chung, Byung-Gook Park, Jong Duk Lee, 2004 .

Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory

Il Han Park, Byung-Gook Park, Seongjae Cho, 2009, SDM 2009.

A boosted common source line program scheme in channel stacked NAND flash memory with layer selection by multilevel operation

Sang-Ho Lee, Byung-Gook Park, Dae Woong Kwon, 2017, 2017 Silicon Nanoelectronics Workshop (SNW).

Integrated neuron circuit for implementing neuromorphic system with synaptic device

Byung-Gook Park, Hyungjin Kim, Jeong-Jun Lee, 2017 .

Unsupervised Online Learning With Multiple Postsynaptic Neurons Based on Spike-Timing-Dependent Plasticity Using a TFT-Type NOR Flash Memory Array pdf

Byung-Gook Park, Jong-Ho Lee, Chul-Heung Kim, 2018, ArXiv.

A new linearity measurement algorithm for sub-micron microwave cmos

Woo Young Choi, Byung-Gook Park, Jong Duk Lee, 2003, Proceedings of the 20th IEEE Instrumentation Technology Conference (Cat. No.03CH37412).

2-bit/Cell Split Gate Flash Memory with Double Gate

Il Han Park, Byung-Gook Park, Jong Duk Lee, 2007 .

Fabrication of 0.1um Buried Channel and Surface Channel pMOSFETs

Byung-Gook Park, Jong Duk Lee, Tae Jong Yoo, 1997 .

Junction Leakage Characteristics of Shallow Trench Isolation (STI) with Nitrogen Pile-Up Sidewall Oxide(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)

Woo Young Choi, Byung-Gook Park, Jong Duk Lee, 2003 .

Analysis on Program Disturbance in Channel-Stacked NAND Flash Memory With Layer Selection by Multilevel Operation

Sang-Ho Lee, Byung-Gook Park, Dae Woong Kwon, 2016, IEEE Transactions on Electron Devices.

Neuromorphic Technology Based on Charge Storage Memory Devices

Tackhwi Lee, Byung-Gook Park, Jong-Ho Lee, 2018, 2018 IEEE Symposium on VLSI Technology.

Implementation of Boolean Logic Functions in Charge Trap Flash for In-Memory Computing

Byung-Gook Park, Yoon Young Kim, Jaehong Lee, 2019, IEEE Electron Device Letters.

Various Flash Memory Devices of Novel Design

Byung-Gook Park, Jong Duk Lee, Jang-Gn Yun, 2009 .

A Vertical 4-Bit SONOS Flash Memory and a Unique 3-D Vertical nor Array Structure

Hyungcheol Shin, Il Han Park, Byung-Gook Park, 2010, IEEE Transactions on Nanotechnology.

Characterization and Design Consideration of 80-nm Self-Aligned N-/P-Channel I-MOS Devices

Woo Young Choi, Byung-Gook Park, Jong Duk Lee, 2006 .

Method to Mitigate Threshold Voltage and ON-Cell Current Variation Caused by Cell Gate Length Fluctuation in NAND Flash Memory with Virtual Source and Drain

Byung-Gook Park, Joo Yun Seo, Se-Hwan Park, 2012 .

Spiking Neural Network Using Synaptic Transistors and Neuron Circuits for Pattern Recognition With Noisy Images

Byung-Gook Park, Sangdoo Yun, Hyungjin Kim, 2018, IEEE Electron Device Letters.

Novel Tunneling Field-Effect Transistor with Sigma-Shape Embedded SiGe Sources and Recessed Channel

Min-Chul Sun, Byung-Gook Park, Hyungjin Kim, 2013, IEICE Trans. Electron..

Novel 3-D stacked NAND flash string without body cross-talk effect

Byung-Gook Park, Jong-Ho Lee, Min-Kyu Jeong, 2010, 2010 IEEE International Memory Workshop.

3D NAND flash memory with laterally-recessed channel (LRC) and connection gate architecture

Byung-Gook Park, Jong Duk Lee, Jang-Gn Yun, 2011 .

Effects of electrical stress on mid-gap interface trap density and capture cross sections in n-MOSFETs characterized by pulsed interface probing measurements

In Man Kang, Byung-Gook Park, Jong Duk Lee, 2004, Microelectron. Reliab..

Memory characteristics improvement encouraged by the shape of narrow drain in cone SONOS memory structure

Il Han Park, Byung-Gook Park, Jong Duk Lee, 2008, 2008 IEEE Silicon Nanoelectronics Workshop.

Circuit-level simulation of resistive-switching random-access memory cross-point array based on a highly reliable compact model

Byung-Gook Park, Seongjae Cho, Min-Hwi Kim, 2018 .

Program scheme using common source lines in channel stacked NAND flash memory with layer selection by multilevel operation

Byung-Gook Park, Dae Woong Kwon, Sang-Ho Lee, 2017 .

Highly Reliable Inference System of Neural Networks Using Gated Schottky Diodes

Byung-Gook Park, Jong-Ho Lee, Sung-Tae Lee, 2019, IEEE Journal of the Electron Devices Society.

A new 50-nm nMOSFET with side-gates for virtual source-drain extensions

Byung-Gook Park, Jong Duk Lee, Byung Yong Choi, 2002 .

Design and simulation of folded split gate SONOS memory

Il Han Park, Byung-Gook Park, Jong Duk Lee, 2008, 2008 IEEE Silicon Nanoelectronics Workshop.

LAyer Selection by ERase (LASER) With an Etch-Through-Spacer Technique in a Bit-Line Stacked 3-D nand Flash Memory Array

Byung-Gook Park, Se Hwan Park, Jang-Gn Yun, 2011, IEEE Transactions on Electron Devices.

A New Programming Method to Alleviate the Program Speed Variation in Three-Dimensional Stacked Array NAND Flash Memory

Byung-Gook Park, Joo Yun Seo, Yoon Kim, 2014 .

Back biasing effects in a feedback steep switching device with charge spacer

Byung-Gook Park, Dae Woong Kwon, Hyungjin Kim, 2016, 2016 IEEE Silicon Nanoelectronics Workshop (SNW).

Extracting accurate position and energy level of oxide trap generating random telegraph noise(RTN) in recessed channel MOSFET's

Hyungcheol Shin, Byung-Gook Park, Gyoyoung Jin, 2010, 2010 Proceedings of the European Solid State Device Research Conference.

A New Capacitorless 1T DRAM Cell: Surrounding Gate MOSFET With Vertical Channel (SGVC Cell)

Hyungcheol Shin, Il Han Park, Kangyoon Lee, 2007, IEEE Transactions on Nanotechnology.

MOS varactor modeling for mm-Wave applications

In Man Kang, Hyungcheol Shin, Hakchul Jung, 2008, 2008 Asia-Pacific Microwave Conference.

Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design

Hyungcheol Shin, Jongwook Jeon, Byung-Gook Park, 2009, IEICE Trans. Electron..

Resistive Switching Characteristics of Silicon Nitride-Based RRAM Depending on Top Electrode Metals

Byung-Gook Park, Seongjae Cho, Min-Hwi Kim, 2015, IEICE Trans. Electron..

A Novel Sensing Scheme for Reliable Read Operation of Ultrathin-Body Vertical nand Flash Memory Devices

Byung-Gook Park, Seongjae Cho, 2011, IEEE Transactions on Electron Devices.

Design optimization of an optically drivable heterogeneous MOSFET with silicon compatibility

S. J. Ben Yoo, James S. Harris, Byung-Gook Park, 2013, Photonics West - Optoelectronic Materials and Devices.

Investigation of Current Degradation Induced by Silicide Source/Drain in the nanowire NAND Flash Memory

Byung-Gook Park, Dae Woong Kwon, Seongjae Cho, 2010 .

3-D Stacked Synapse Array Based on Charge-Trap Flash Memory for Implementation of Deep Neural Networks

Byung-Gook Park, Jong-Ho Lee, Hui Tae Kwon, 2019, IEEE Transactions on Electron Devices.

Nanosculpture: Three-dimensional CMOS device structures for the ULSI era

Byung-Gook Park, Seongjae Cho, Hoon Jeong, 2009, Microelectron. J..

System-Level Simulation of Hardware Spiking Neural Network Based on Synaptic Transistors and I&F Neuron Circuits

Byung-Gook Park, Hyungjin Kim, Jeong-Jun Lee, 2018, IEEE Electron Device Letters.

Fabrication Process of Cone SONOS Memory Structure

Il Han Park, Byung-Gook Park, Jong Duk Lee, 2008 .

Effects of Current Spreading in GaN-based Light-emitting Diodes Using ITO Spreading Pad

Byung-Gook Park, Jang Hyun Kim, Euyhwan Park, 2015 .

DIBL-Induced Program Disturb Characteristics in 32-nm NAND Flash Memory Array

Myounggon Kang, Hyungcheol Shin, Il Han Park, 2011, IEEE Transactions on Electron Devices.

Characterization and Design Consideration of I-MOS Devices

Woo Young Choi, Byung-Gook Park, Jong Duk Lee, 2006 .

Anomalous Subthreshold Characteristics due to Localized Pileup of Channel Dopants in Submicron MOSFET`s

Hong Shick Min, Byung-Gook Park, H. S. Shin, 1997 .

Dual-Poly Gate Surface Channel 0.1mm CMOSFETs

Byung-Gook Park, Jong Duk Lee, Hyouk Man Kwon, 1997 .

Surface Treatment of Ge Grown Epitaxially on Si by Ex-Situ Annealing for Optical Computing by Ge Technology

Byung-Gook Park, Seongjae Cho, James S. Harris, 2014 .

Process Considerations for 80-GHz High-Performance p-i-n Silicon Photodetector for Optical Interconnect

Min-Chul Sun, James S. Harris, Byung-Gook Park, 2012 .

Cone-Type SONOS Flash Memory

Hyungcheol Shin, Il Han Park, Byung-Gook Park, 2009, IEEE Electron Device Letters.

Analytical Noise Parameter Model of Short-Channel RF MOSFETs

Jongwook Jeon, Byung-Gook Park, Jong Duk Lee, 2007 .

Complementary self-biased scheme for the robust design of CMOS/SET hybrid multi-valued logic

Ki-Whan Song, Sang-Hoon Lee, Byung-Gook Park, 2003, 33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings..

Integrate-and-Fire Neuron Circuit and Synaptic Device using Floating Body MOSFET with Spike Timing- Dependent Plasticity

Byung-Gook Park, Min-Woo Kwon, Jungjin Park, 2015 .

Dot Product Engine Using Gated Schottky Diode with Quantized Weight

Byung-Gook Park, Jong-Ho Lee, Sung-Tae Lee, 2019, 2019 Electron Devices Technology and Manufacturing Conference (EDTM).

Simulation Study on Silicon-Based Floating Body Synaptic Transistor with Short- and Long-Term Memory Functions and Its Spike Timing-Dependent Plasticity

Min-Chul Sun, Byung-Gook Park, Seongjae Cho, 2016 .

Technical Program Committee Chair’s Message

Byung-Gook Park, Yoshinao Shiraki, 2007 .

Stacked-nanowire device with virtual source/drain (SD-VSD) for 3D NAND flash memory application

Byung-Gook Park, Seongjae Cho, Jang-Gn Yun, 2011 .

SET/CMOS hybrid process and multiband filtering circuits

Ki-Whan Song, Young-Wug Kim, Yong Kyu Lee, 2005 .

Arch NAND Flash Memory Array With Improved Virtual Source/Drain Performance

Hyungcheol Shin, Byung-Gook Park, Seongjae Cho, 2010, IEEE Electron Device Letters.

Boolean logic circuit implementaion using multi-input floating-body MOSFET

Byung-Gook Park, Hyungjin Kim, Min-Woo Kwon, 2015, 2015 Silicon Nanoelectronics Workshop (SNW).

Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation

Byung-Gook Park, Jong Duk Lee, Seongjae Cho, 2009, IEICE Trans. Electron..

Dumbbell-shaped Nanowire with Body Contact Region for Three Dimensional (3D) NAND Flash Memory Application

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2010 .

Effects of Conductive Defects on Unipolar RRAM for the Improvement of Resistive Switching Characteristics

Byung-Gook Park, Jeong-Hoon Oh, Hyungjin Kim, 2012, IEICE Trans. Electron..

Investigation on Suppression of Nickel-Silicide Formation By Fluorocarbon Reactive Ion Etch (RIE) and Plasma-Enhanced Deposition

Min-Chul Sun, Byung-Gook Park, Hyunwoo Kim, 2013 .

An analytical channel thermal noise model for deep-submicron MOSFETs with short channel effects

Jongwook Jeon, Byung-Gook Park, Jong Duk Lee, 2007 .

Enhanced Program/Erase Characteristic of Arch Shaped SONOS Flash Memory

Il Han Park, Byung-Gook Park, Jong Duk Lee, 2008 .

Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2007, IEICE Trans. Electron..

Comparative Study on Top- and Bottom-Source Vertical-Channel Tunnel Field-Effect Transistors

Min-Chul Sun, Byung-Gook Park, Hyungjin Kim, 2012, IEICE Trans. Electron..

Layer Selection by Multi-Level Permutation in 3-D Stacked NAND Flash Memory

Sang-Ho Lee, Byung-Gook Park, Dae Woong Kwon, 2016, IEEE Electron Device Letters.

Comprehensive analysis of retention characteristics in 3-D NAND flash memory cells with tube-type poly-Si channel structure

Byung-Gook Park, Jong-Ho Lee, Sung-Min Joe, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

L-Shaped Tunneling Field-Effect Transistors for Complementary Logic Applications

Hyungcheol Shin, Min-Chul Sun, Woo Young Choi, 2013, IEICE Trans. Electron..

Reduction of Current Crowding in InGaN-based Blue Light-Emitting Diodes by Modifying Metal Contact Geometry

Byung-Gook Park, Jang Hyun Kim, Garam Kim, 2014 .

First-principle Study for More Accurate Optical and Electrical Characterization of Ge1-xSnx Alloy for Si and Group-IV Device Applications

Byung-Gook Park, Seongjae Cho, James S. Harris, 2017 .

Dependence of program and erase speed on bias conditions for fully depleted channel of vertical NAND flash memory devices

Byung-Gook Park, Seongjae Cho, Yoon Kim, 2009, 2009 10th Annual Non-Volatile Memory Technology Symposium (NVMTS).

Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme

Yoon Kim, Byung-Gook Park, Jong Duk Lee, 2008, IEICE Trans. Electron..

Integrate-and-fire neuron circuit using positive feedback field effect transistor for low power operation

Kyungchul Park, Byung-Gook Park, Seongjae Cho, 2018, Journal of Applied Physics.

Ge-on-Si photodetector with novel metallization schemes for on-chip optical interconnect

Byung-Gook Park, Seongjae Cho, Sae-Kyoung Kang, 2015, 2015 International Symposium on Consumer Electronics (ISCE).

Suppression of Read Disturb Fail Caused by Boosting Hot Carrier Injection Effect for 3-D Stack NAND Flash Memories

Byung-Gook Park, Jong-Ho Lee, Jung-Kyu Lee, 2014, IEEE Electron Device Letters.

A Simple Figure of Merit of RF MOSFET for Low-Noise Amplifier Design

Hyungcheol Shin, Hee-Sauk Jhon, Jongwook Jeon, 2008, IEEE Electron Device Letters.

Full-Swing Pentacene Organic Inverter with Long-Channel Driver and Short-Channel Load

Byung-Gook Park, Jong Duk Lee, Dong-Wook Park, 2006 .

Crystallization and Characterization of GeSn Deposited on Si with Ge Buffer Layer by Low-temperature Sputter Epitaxy

Dongsun Seo, Il Hwan Cho, Byung-Gook Park, 2016 .

Fabrication and characterization of fin SONOS flash memory with separated double-gate structure

Hyungcheol Shin, Il Han Park, Byung-Gook Park, 2008 .

Gated Twin-Bit (GTB) nonvolatile memory device and its operation

Hyungcheol Shin, Il Han Park, Byung-Gook Park, 2008, 2008 IEEE Silicon Nanoelectronics Workshop.

Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2009, IEICE Trans. Electron..

First demonstration of diode-type 3-D NAND flash memory string having super-steep switching slope

Byung-Gook Park, Jong-Ho Lee, Sung-Ho Bae, 2017, 2017 Symposium on VLSI Technology.

Highly compact and accurate circuit-level macro modeling of gate-all-around charge-trap flash memory

Byung-Gook Park, Seongjae Cho, Seung-Hyun Kim, 2016 .

Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices

Hyungcheol Shin, Byung-Gook Park, Seongjae Cho, 2010, IEICE Trans. Electron..

A new read method suppressing effect of random telegraph noise in NAND flash memory by using hysteretic characteristic

Byung-Gook Park, Kyoung-Rok Han, Jong-Ho Lee, 2013, 2013 Symposium on VLSI Technology.

Study on Threshold Voltage Control of Tunnel Field-Effect Transistors Using VT-Control Doping Region

Min-Chul Sun, Byung-Gook Park, Hyungjin Kim, 2012, IEICE Trans. Electron..

Dependency of Program Efficiency on Implementation Conditions for NOR Type Silicon-on-Insulator (SOI) Flash Memory

Il Han Park, Byung-Gook Park, Jong Duk Lee, 2008 .

Analytic Threshold Voltage Model of Recessed Channel MOSFETs

Byung-Gook Park, Hyungcheol Shin, Yeonsung Kang, 2010 .

Circuit-level macro modeling of charge-trap flash memory array

Byung-Gook Park, Seongjae Cho, Lee Sangho, 2017 .

Neuron Circuit Using a Thyristor and Inter-neuron Connection with Synaptic Devices

Byung-Gook Park, Rajeev Ranjan, Min-Woo Kwon, 2015 .

Hardware-Based Spiking Neural Network Using a TFT-Type AND Flash Memory Array Architecture Based on Direct Feedback Alignment

Byung-Gook Park, Jong-Ho Lee, Dongseok Kwon, 2021, IEEE Access.

Pulse-Width Modulation Neuron Implemented by Single Positive-Feedback Device pdf

Byung-Gook Park, Jong-Ho Lee, Jong-Ho Bae, 2021, ArXiv.

Integrate-and-Fire Neuron Circuit With Synaptic Off-Current Blocking Operation

Byung-Gook Park, Jong-Ho Lee, Sungmin Hwang, 2021, IEEE Access.

On-chip adaptive matching learning with charge-trap synapse device and ReLU activation circuit

Byung-Gook Park, Sungjun Kim, Hyun-Seok Choi, 2021, Solid-State Electronics.

Spiking Neural Networks With Time-to-First-Spike Coding Using TFT-Type Synaptic Device Model

Byung-Gook Park, Jong-Ho Lee, Jong-Ho Bae, 2021, IEEE Access.

On-chip trainable hardware-based deep Q-networks approximating a backpropagation algorithm

Byung-Gook Park, Jong-Ho Lee, Jong-Ho Bae, 2021, Neural Computing and Applications.

Quantized Weight Transfer Method Using Spike-Timing-Dependent Plasticity for Hardware Spiking Neural Network

Byung-Gook Park, Sungmin Hwang, Hyungjin Kim, 2021, Applied Sciences.

Selected Bit-Line Current PUF: Implementation of Hardware Security Primitive Based on a Memristor Crossbar Array

Wookyung Sun, Byung-Gook Park, Geun Ho Lee, 2021, IEEE Access.

Nonlinear and multilevel resistive switching memory in Ni/Si3N4/Al2O3/TiN structures

Byung-Gook Park, Sungjun Kim, 2016 .

Dynamic bias temperature instability-like behaviors under Fowler–Nordheim program/erase stress in nanoscale silicon-oxide-nitride-oxide-silicon memories

Byung-Gook Park, Dong Myong Kim, Jong Duk Lee, 2008 .

Design Optimization of a Type-I Heterojunction Tunneling Field-Effect Transistor (I-HTFET) for High Performance Logic Technology

Min-Chul Sun, James S. Harris, Byung-Gook Park, 2011 .

Pulse area dependent gradual resistance switching characteristics of CMOS compatible SiN x -based resistive memory

Byung-Gook Park, Seongjae Cho, Sungjun Kim, 2017 .

Silicon-Based Floating-Body Synaptic Transistor With Frequency-Dependent Short- and Long-Term Memories

Byung-Gook Park, Jong-Ho Lee, Min-Woo Kwon, 2016, IEEE Electron Device Letters.

Electron trap density distribution of Si-rich silicon nitride extracted using the modified negative charge decay model of silicon-oxide-nitride-oxide-silicon structure at elevated temperatures

Hyungcheol Shin, Byung-Gook Park, Il Han Park, 2006 .

Dynamic exclusive-OR gate based on gate-induced Si island single-electron transistor

Byung-Gook Park, Jong Duk Lee, Dae Hwan Kim, 2002 .

3-D Floating-Gate Synapse Array With Spike-Time-Dependent Plasticity

Byung-Gook Park, Sungjun Kim, Kyung-Chang Ryoo, 2018, IEEE Transactions on Electron Devices.

Effect of Oxidation Amount on Gradual Switching Behavior in Reset Transition of Al/TiO2-Based Resistive Switching Memory and Its Mechanism for Multilevel Cell Operation

Byung-Gook Park, Sunghun Jung, Kyung-Chang Ryoo, 2012 .

Compact modeling of silicon nanowire MOSFET for radio frequency applications

In Man Kang, Byung-Gook Park, Seongjae Cho, 2011 .

Analog Synaptic Behavior of a Silicon Nitride Memristor.

Byung-Gook Park, Sungjun Kim, Yao-Feng Chang, 2017, ACS applied materials & interfaces.

Tuning resistive switching parameters in Si3N4-based RRAM for three-dimensional vertical resistive memory applications

Byung-Gook Park, Seongjae Cho, Sunghun Jung, 2016 .

Novel U-Shape Resistive Random Access Memory Structure for Improving Resistive Switching Characteristics

Byung-Gook Park, Sunghun Jung, Kyung-Chang Ryoo, 2011 .

Investigation of Thermal Noise Factor in Nanoscale MOSFETs

Hyungcheol Shin, Jongwook Jeon, Byung-Gook Park, 2010 .

30 nm self-aligned FinFET with large source/drain fan-out structure

Byung-Gook Park, Byung Yong Choi, Jong Duk Lee, 2003 .

An Analytic Current–Voltage Equation for Top-Contact Organic Thin Film Transistors Including the Effects of Variable Series Resistance

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2008 .

A New Noise Parameter Model of Short-Channel MOSFETs

In Man Kang, Hyungcheol Shin, Jongwook Jeon, 2007, 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium.

Vertical type double gate tunnelling FETs with thin tunnel barrier

Byung-Gook Park, Sang Wan Kim, Hyunwoo Kim, 2015 .

Effects of channel doping concentration and fin dimension variation on self-boosting of channel potential in NAND-type SONOS flash memory array based on bulk-FinFETs

Il Hwan Cho, Byung-Gook Park, Seongjae Cho, 2010 .

A practical SPICE model based on the physics and characteristics of realistic single-electron transistors

Byung-Gook Park, Jeong-Taek Kong, Jong Duk Lee, 2002 .

Investigation of Field Concentration Effects in Arch Gate Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory

Byung-Gook Park, Seongjae Cho, Jang-Gn Yun, 2010 .

Reduction of hot-carrier generation in 0.1-μm recessed channel nMOSFET with laterally graded channel doping profile

Byung-Gook Park, Jong Duk Lee, Jeongho Lyu, 1997 .

High-Density and Near-Linear Synaptic Device Based on a Reconfigurable Gated Schottky Diode

Byung-Gook Park, Jong-Ho Lee, Suhwan Lim, 2017, IEEE Electron Device Letters.

Improving the Cell Characteristics Using SiN Liner at Active Edge in 4 Gbits NAND Flash Memories

Hyungcheol Shin, Byung-Gook Park, Daewoong Kang, 2008 .

Areal and Structural Effects on Oxide-Based Resistive Random Access Memory Cell for Improving Resistive Switching Characteristics

Byung-Gook Park, Sunghun Jung, Kyung-Chang Ryoo, 2012 .

Neuromorphic System Based on CMOS Inverters and Si-Based Synaptic Device.

Byung-Gook Park, Min-Woo Kwon, Hyungjin Kim, 2016, Journal of nanoscience and nanotechnology.

Design Guideline of Si-Based L-Shaped Tunneling Field-Effect Transistors

Min-Chul Sun, Woo Young Choi, Byung-Gook Park, 2012 .

Ultralow power switching in a silicon-rich SiNy/SiNx double-layer resistive memory device.

Byung-Gook Park, Sungjun Kim, Jong-Ho Lee, 2017, Physical chemistry chemical physics : PCCP.

Effects of germanium incorporation on optical performances of silicon germanium passive devices for group-IV photonic integrated circuits

James S. Harris, Robert Sinclair, Byung-Gook Park, 2014 .

A capacitor-less 1T-DRAM cell with vertical surrounding gates using gate-induced drain-leakage (GIDL) current

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2008, 2008 IEEE Silicon Nanoelectronics Workshop.

Channel doping concentration and fin width effects on self-boosting in NAND-type SONOS flash memory array based on bulk-FinFETs

Il Hwan Cho, Byung-Gook Park, Seongjae Cho, 2009, 2009 IEEE Nanotechnology Materials and Devices Conference.

Nanoscale Poly-Si Line Formation and Its Uniformity

Byung-Gook Park, Jong Duk Lee, Suk Kang Sung, 2001 .

Investigation of mobility in twin silicon nanowire MOSFETs (TSNWFETs)

Hyungcheol Shin, Byung-Gook Park, Donggun Park, 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

Room-temperature electroluminescence from germanium in an Al(0.3)Ga(0.7)As/Ge heterojunction light-emitting diode by Γ-valley transport.

Byung-Gook Park, Seongjae Cho, Euijoon Yoon, 2012, Optics express.

Pentacene OTFTs with PVA gate insulators on a flexible substrate

Byung-Gook Park, Jin Wook Kim, Jong Duk Lee, 2004 .

100-nm n-/p-channel I-MOS using a novel self-aligned structure

Byung-Gook Park, Young June Park, Jong Duk Lee, 2005 .

Novel Tunneling Devices with Multi-Functionality

Byung-Gook Park, Jong Duk Lee, Woo Young Choi, 2007 .

Improved multi-level capability in Si3N4-based resistive switching memory using continuous gradual reset switching

Byung-Gook Park, Sungjun Kim, 2017 .

Scaling Effect on Silicon Nitride Memristor with Highly Doped Si Substrate.

Byung-Gook Park, Seongjae Cho, Sunghun Jung, 2018, Small.

Low hysteresis pentacene thin-film transistors using SiO2/cross-linked poly(vinyl alcohol) gate dielectric

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2006 .

Realistic single-electron transistor modeling and novel CMOS/SET hybrid circuits

Ki-Whan Song, Byung-Gook Park, Jong Duk Lee, 2003, 2003 Third IEEE Conference on Nanotechnology, 2003. IEEE-NANO 2003..

Integrate-and-fire neuron circuit and synaptic device with a floating body MOSFET

Byung-Gook Park, Jong-Ho Lee, Min-Woo Kwon, 2014 .

Neuronal dynamics in HfOx/AlOy-based homeothermic synaptic memristors with low-power and homogeneous resistive switching.

Yi Li, Byung-Gook Park, Sungjun Kim, 2018, Nanoscale.

Gradual bipolar resistive switching in Ni/Si3N4/n+-Si resistive-switching memory device for high-density integration and low-power applications

Byung-Gook Park, Seongjae Cho, Sunghun Jung, 2015 .

Electrical characteristics of FinFET with vertically nonuniform source/drain doping profile

Byung-Gook Park, Byung Yong Choi, Jong Duk Lee, 2002 .

Stable threshold voltage extraction using Tikhonov's regularization theory

Byoungho Lee, Byung-Gook Park, Jong Duk Lee, 2004 .

Nanoscale Multi-Line Patterning Using Sidewall Structure

Byung-Gook Park, Jong Duk Lee, Dae Hwan Kim, 2002 .

Synchronous mirror delay for zero- and multi-phase locking

Byung-Gook Park, Jong Duk Lee, Yong-jin Yoon, 2002 .

A Low-Energy High-Density Capacitor-Less I&F Neuron Circuit Using Feedback FET Co-Integrated With CMOS

Byung-Gook Park, Junil Lee, Min-Woo Kwon, 2019, IEEE Journal of the Electron Devices Society.

Synaptic Characteristics of Amorphous Boron Nitride-based Memristors on a Highly Doped Silicon Substrate for Neuromorphic Engineering.

Byung-Gook Park, Chandreswar Mahata, Sungjun Kim, 2020, ACS applied materials & interfaces.

Accurate Extraction of Mobility, Effective Channel Length, and Source/Drain Resistance in 60 nm MOSFETs

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2007 .

Analytical modeling of field-induced interband tunneling-effect transistors and its application

Ki-Whan Song, Byung-Gook Park, Seung-Hwan Song, 2006 .

The effects of deuterium annealing on the reduction of dark currents in the CMOS APS

Hyungcheol Shin, S. S. Park, Byung-Gook Park, 2004, IEEE Transactions on Electron Devices.

Body Doping Profile of Select Device to Minimize Program Disturbance in Three-Dimensional Stack NAND Flash Memory

Byung-Gook Park, Jong-Ho Lee, Byeong-In Choe, 2013 .

Silicon-compatible compound semiconductor tunneling field-effect transistor for high performance and low standby power operation

In Man Kang, James S. Harris, Byung-Gook Park, 2011 .

25nm Programmable Virtual Source/Drain MOSFETs Using a Twin SONOS Memory Structure

Byung-Gook Park, Donggun Park, Young June Park, 2005, 2005 International Semiconductor Device Research Symposium.

80nm self-aligned complementary I-MOS using double sidewall spacer and elevated drain structure and its applicability to amplifiers with high linearity

Byung-Gook Park, Young June Park, Byung Yong Choi, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Overflow Handling Integrate-and-Fire Silicon-on-Insulator Neuron Circuit Incorporating a Schmitt Trigger Implemented by Back-Gate Effect.

Byung-Gook Park, Young Suh Song, Byung-Gook Park, 2019, Journal of nanoscience and nanotechnology.

Single-electron transistors fabricated with sidewall spacer patterning

Ki-Whan Song, Byung-Gook Park, Jong Duk Lee, 2003 .

Analog Complementary Metal-Oxide-Semiconductor Integrate-and-Fire Neuron Circuit for Overflow Retaining in Hardware Spiking Neural Networks.

Byung-Gook Park, Jong-Ho Lee, Min-Woo Kwon, 2020, Journal of nanoscience and nanotechnology.

Extraction of trap energy and location from random telegraph noise in gate leakage current (Ig RTN) of metal–oxide semiconductor field effect transistor (MOSFET)

Hyungcheol Shin, Byung-Gook Park, Heung-Jae Cho, 2010 .

70-nm impact-ionization metal-oxide-semiconductor (I-MOS) devices integrated with tunneling field-effect transistors (TFETs)

Woo Young Choi, Byung-Gook Park, Young June Park, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Low-pressure, low-temperature hydrogen annealing for nanoscale silicon fin rounding

Byung-Gook Park, Seongjae Cho, Il Han Park, 2006, 2006 IEEE Nanotechnology Materials and Devices Conference.

Threshold Voltage Fluctuation by Random Telegraph Noise in Floating Gate nand Flash Memory String

Hyungcheol Shin, Byung-Gook Park, Young June Park, 2011, IEEE Transactions on Electron Devices.

Highly scalable and reliable 2-bit/cell SONOS memory transistor beyond 50nm NVM technology using outer sidewall spacer scheme with damascene gate process

Byung-Gook Park, Chang Woo Oh, Sung Hwan Kim, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Variation of the spacer layer between two resonant tunneling diodes

James S. Harris, Byung-Gook Park, Kevin L. Lear, 1989 .

Multi-Level Threshold Voltage Setting Method of String Select Transistors for Layer Selection in Channel Stacked NAND Flash Memory

Byung-Gook Park, Dae Woong Kwon, Joo Yun Seo, 2015, IEEE Electron Device Letters.

Diode-Type NAND Flash Memory Cell String Having Super-Steep Switching Slope Based on Positive Feedback

Myounggon Kang, Byung-Gook Park, Jong-Ho Lee, 2016, IEEE Transactions on Electron Devices.

Understanding rectifying and nonlinear bipolar resistive switching characteristics in Ni/SiNx/p-Si memory devices

Byung-Gook Park, Sungjun Kim, Yao-Feng Chang, 2017 .

Full-Swing a-IGZO Inverter With a Depletion Load Using Negative Bias Instability Under Light Illumination

Hyungcheol Shin, Byung-Gook Park, Hyuck-In Kwon, 2012, IEEE Electron Device Letters.

3-D stacked active layers and vertical gate NAND flash string with single-crystal Si channel by adopting Si/SiGe selective etch process

Hyungcheol Shin, Byung-Gook Park, Hyuck-In Kwon, 2010, 2010 Silicon Nanoelectronics Workshop.

Single-electron transistors based on gate-induced Si island for single-electron logic application

Byung-Gook Park, Jong Duk Lee, Dae Hwan Kim, 2002 .

Effect of traps on transient bit-line current behavior in word-line stacked nand flash memory with poly-Si body

Byung-Gook Park, Jong-Ho Lee, Sung-Min Joe, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Enhancement of Memory Performance Using Doubly Stacked Si-Nanocrystal Floating Gates Prepared by Ion Beam Sputtering in UHV

Byung-Gook Park, Il Han Park, Kyu Il Han, 2007, IEEE Transactions on Electron Devices.

Dual Functions of V/SiOx/AlOy/p++Si Device as Selector and Memory

Byung-Gook Park, Sungjun Kim, Yao-Feng Chang, 2018, Nanoscale Research Letters.

Optimum Design of Junctionless MOSFET Based on Silicon Nanowire Structure and Analysis on Basic RF Characteristics

Byung-Gook Park, Kyung-Rok Kim, Seong-Jae Cha, 2010 .

Nano-cone resistive memory for ultralow power operation.

Byung-Gook Park, Seongjae Cho, Sunghun Jung, 2017, Nanotechnology.

Study on Time Constants of Random Telegraph Noise in Gate Leakage Current Through Hot-Carrier Stress Test

Hyungcheol Shin, Byung-Gook Park, Heung-Jae Cho, 2010, IEEE Electron Device Letters.

Integration process of impact-ionization metal-oxide-semiconductor devices with tunneling field-effect-transistors and metal-oxide-semiconductor field-effect transistors

Byung-Gook Park, Jong Duk Lee, Woo Young Choi, 2007 .

Independent Double-Gate Fin SONOS Flash Memory Fabricated With Sidewall Spacer Patterning

Hyungcheol Shin, Byung-Gook Park, Il Han Park, 2009, IEEE Transactions on Electron Devices.

Multi-level vertical channel SONOS nonvolatile memory on SOI

Byung-Gook Park, Sang Hun Lee, Jong Duk Lee, 2002, VLSIT 2002.

Resistive switching characteristics of Si3N4-based resistive-switching random-access memory cell with tunnel barrier for high density integration and low-power applications

Byung-Gook Park, Seongjae Cho, Sunghun Jung, 2015 .

Modeling and Parameter Extraction for the Series Resistance in Thin-Film Transistors

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2009 .

Space Program Scheme for 3-D NAND Flash Memory Specialized for the TLC Design

Byung-Gook Park, Jong-Ho Lee, Jong-Ho Bae, 2018, 2018 IEEE Symposium on VLSI Technology.

Ultra-energy-efficient analog-to-digital converters based on single-electron transistor/CMOS hybrid technology for biomedical applications

Byung-Gook Park, Dong Myong Kim, In-Young Chung, 2009 .

Side-Gate Design Optimization of 50 nm MOSFETs with Electrically Induced Source/Drain

Byung-Gook Park, Byung Yong Choi, Jong Duk Lee, 2002 .

Stable extraction of linearity (V/sub IP3/) for nanoscale RF CMOS devices

Byung-Gook Park, Byung Yong Choi, Jong Duk Lee, 2004 .

A new fabrication method for self-aligned nanoscale I-MOS (impact-ionization MOS)

Byung-Gook Park, Byung Yong Choi, Jong Duk Lee, 2004, Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC..

An Accurate Compact Model Considering Direct-Channel Interference of Adjacent Cells in Sub-30-nm nand Flash Technologies

Myounggon Kang, Hyungcheol Shin, Byung-Gook Park, 2012, IEEE Electron Device Letters.

Pentacene‐based thin film transistors with improved mobility characteristics using hybrid gate insulator

Byung-Gook Park, Jong Duk Lee, Sung Hun Jin, 2005 .

Fabrication of asymmetric independent dual-gate FinFET using sidewall spacer patterning and CMP processes

Min-Chul Sun, Byung-Gook Park, Jong-Ho Lee, 2018 .

Fully Si compatible SiN resistive switching memory with large self-rectification ratio

Byung-Gook Park, Seongjae Cho, Sungjun Kim, 2016 .

RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs

In Man Kang, Byung-Gook Park, Seongjae Cho, 2011, IEEE Transactions on Electron Devices.

Investigation of bipolar resistive switching characteristics in Si 3 N 4 -based RRAM with metal-insulator-silicon structure

Byung-Gook Park, Sunghun Jung, Sungjun Kim, 2014 .

Scalable embedded Ge-junction vertical-channel tunneling field-effect transistor for low-voltage operation

Hyungcheol Shin, Min-Chul Sun, Byung-Gook Park, 2010, 2010 IEEE Nanotechnology Materials and Devices Conference.

Ultra fine multi-line patterning based on sidewall patterning technique

Byung-Gook Park, Jong Duk Lee, Suk-Kang Sung, 2001, Digest of Papers. Microprocesses and Nanotechnology 2001. 2001 International Microprocesses and Nanotechnology Conference (IEEE Cat. No.01EX468).

Channel-stacked NAND flash memory with layer selection by multi-level operation (LSM)

Byung-Gook Park, Joo Yun Seo, Jong-Ho Lee, 2013, 2013 IEEE International Electron Devices Meeting.

Fabrication of single-electron tunneling transistors with an electrically formed Coulomb island in a silicon-on-insulator nanowire

Byung-Gook Park, Jong Duk Lee, Dae Hwan Kim, 2002 .

Program/Erase Model of Nitride-Based NAND-Type Charge Trap Flash Memories

Hyungcheol Shin, Byung-Gook Park, Seongjae Cho, 2010 .

Si single-electron transistors with sidewall depletion gates and their application to dynamic single-electron transistor logic

Byung-Gook Park, Jong Duk Lee, Doyeol Ahn, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Demonstration of L-Shaped Tunnel Field-Effect Transistors

Woo Young Choi, Byung-Gook Park, J. Kim, 2016, IEEE Transactions on Electron Devices.

Design optimization of gate-all-around (GAA) MOSFETs

Byung-Gook Park, Jong Duk Lee, Jae Young Song, 2006 .

Comparative Study on Energy-Efficiencies of Single-Electron Transistor-Based Binary Full Adders Including Nonideal Effects

Byung-Gook Park, Dong Myong Kim, In-Young Chung, 2011, IEEE Transactions on Nanotechnology.

Reset Current Reduction with Excellent Filament Controllability by Using Area Minimized and Field Enhanced Unipolar Resistive Random Access Memory Structure

Byung-Gook Park, Sunghun Jung, Kyung-Chang Ryoo, 2012 .

Room Temperature Coulomb Oscillation of a Single Electron Switch with an Electrically Formed Quantum Dot and Its Modeling

Byung-Gook Park, Jong Duk Lee, Dae Hwan Kim, 2000 .

Extended Word-Line NAND Flash Memory

Byung-Gook Park, Il Han Park, Jang-Gn Yun, 2009 .

Characterization of traps in 3-D stacked NAND flash memory devices with tube-type poly-Si channel structure

Byung-Gook Park, Kyoung-Rok Han, Jong-Ho Lee, 2012, 2012 International Electron Devices Meeting.

Unsupervised Online Learning With Multiple Postsynaptic Neurons Based on Spike-Timing-Dependent Plasticity Using a Thin-Film Transistor-Type NOR Flash Memory Array.

Byung-Gook Park, Jong-Ho Lee, Chul-Heung Kim, 2019, Journal of nanoscience and nanotechnology.

Trap Profiling in Nitride Storage Layer in 3-D NAND Flash Memory Using Retention Characteristics and AC- $\text{g}_{\mathrm {m}}$ Method

Byung-Gook Park, Jong-Ho Lee, Sung-Min Joe, 2015, IEEE Electron Device Letters.

Characterization of 2-bit Recessed Channel Memory with Lifted Charge Trapping Node Scheme

Byung-Gook Park, Seongjae Cho, Il Han Park, 2007 .

Compound Semiconductor Tunneling Field-Effect Transistor Based on Ge/GaAs Heterojunction with Tunneling-Boost Layer for High-Performance Operation

In Man Kang, Jae Hwa Seo, Byung-Gook Park, 2013 .

Uniformity improvement by optimization of switching interface in bi-layer unipolar RRAM structure for low power new memory application

Byung-Gook Park, Sunghun Jung, Sungjun Kim, 2011, 2011 International Semiconductor Device Research Symposium (ISDRS).

Pruning for Hardware-Based Deep Spiking Neural Networks Using Gated Schottky Diode as Synaptic Devices.

Byung-Gook Park, Jong-Ho Lee, Suhwan Lim, 2020, Journal of nanoscience and nanotechnology.

Analysis of conduction mechanism in silicon nitride-based RRAM

Hyungcheol Shin, Byung-Gook Park, Sunghun Jung, 2014 .

Effects of conducting defects on resistive switching characteristics of SiNx-based resistive random-access memory with MIS structure

Byung-Gook Park, Seongjae Cho, Sungjun Kim, 2015 .

Reconfigurable Field-Effect Transistor as a Synaptic Device for XNOR Binary Neural Network

Byung-Gook Park, Jong-Ho Lee, Suhwan Lim, 2019, IEEE Electron Device Letters.

Spiking Neural Networks with Unsupervised Learning Based on STDP Using Resistive Synaptic Devices and Analog CMOS Neuron Circuit.

Byung-Gook Park, Sungjun Kim, Min-Woo Kwon, 2018, Journal of nanoscience and nanotechnology.

Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL)

Byung-Gook Park, Seongjae Cho, Meishoku Masahara, 2009, 2009 International Semiconductor Device Research Symposium.

Locally-separated vertical channel SONOS flash memory (LSVC SONOS) for multi-storage and multi-level operation

Byung-Gook Park, Seongjae Cho, Il Han Park, 2008, 2008 IEEE Silicon Nanoelectronics Workshop.

Mixed-Mode Simulation of Nanowire Ge/GaAs Heterojunction Tunneling Field-Effect Transistor for Circuit Applications

In Man Kang, Byung-Gook Park, Seongjae Cho, 2013, IEEE Journal of the Electron Devices Society.

$f_{\max}$ Improvement by Controlling Extrinsic Parasitics in Circuit-Level MOS Transistor

Hyungcheol Shin, Hee-Sauk Jhon, Byung-Gook Park, 2009, IEEE Electron Device Letters.

Design of Thin-Body Double-Gated Vertical-Channel Tunneling Field-Effect Transistors for Ultralow-Power Logic Circuits

Hyungcheol Shin, Min-Chul Sun, Byung-Gook Park, 2012 .

Tuning tunnel barrier in Si3N4-based resistive memory embedding SiO2 for low-power and high-density cross-point array applications

Byung-Gook Park, Sungjun Kim, 2016 .

Adaptive Weight Quantization Method for Nonlinear Synaptic Devices

Byung-Gook Park, Jong-Ho Lee, Suhwan Lim, 2019, IEEE Transactions on Electron Devices.

Twin-bit silicon-oxide-nitride-oxide-silicon (SONOS) memory by inverted sidewall patterning (TSM-ISP)

Byung-Gook Park, Jong Duk Lee, Sang Hoon Lee, 2003 .

Fabrication of Highly Scaled Silicon Nanowire Gate-All-Around Metal–Oxide–Semiconductor Field Effect Transistors by Using Self-Aligned Local-Channel V-gate by Optical Lithography Process

Byung-Gook Park, Jang-Gn Yun, Jae Young Song, 2010 .

A Band-Engineered One-Transistor DRAM With Improved Data Retention and Power Efficiency

Byung-Gook Park, Seongjae Cho, Hyungsoon Shin, 2019, IEEE Electron Device Letters.