Jong Duk Lee

发表

Size efficient low‐noise amplifier for 2.4 GHz ISM‐band transceiver

Hyungcheol Shin, Hee-Sauk Jhon, Hakchul Jung, 2009 .

A Gated Twin-Bit (GTB) Nonvolatile Memory Device and Its Fabrication Method

Hyungcheol Shin, Il Han Park, Byung-Gook Park, 2009, IEEE Transactions on Nanotechnology.

Improving the cell characteristics using arch-active profile in NAND flash memory having 60.nm design rule

Il Han Park, Byung-Gook Park, Jong Duk Lee, 2008 .

PAPER Special Section on Fundamentals and Applications of Advanced Semiconductor Devices Design and Simulation of Asymmetric MOSFETs

Nonmembers, Woo Young Choi, Byung-Gook Park, 2007 .

Programmable virtual source/drain MOSFETs

Hyungcheol Shin, Il Han Park, Chilhee Chung, 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

An Approach to a Small Dot Fabricated with an Etch-back Process

Jin-Ho Kim, Woo Young Choi, Jong Duk Lee, 2006 .

Design of nMOS driving circuits integrated with field emitter arrays

Jong Duk Lee, Chang Woo Oh, Jung Hyun Nam, 1998, Eleventh International Vacuum Microelectronics Conference. IVMC'98 (Cat. No.98TH8382).

Reverse-order source/drain formation with double offset spacer (RODOS) for low-power and high-speed application

Woo Young Choi, Byung-Gook Park, Jong Duk Lee, 2003 .

Poly-Crystalline Silicon Field Emitter Arrays Applied to Vacuum Fluorescent Display

Jong Duk Lee, Sang Jik Kwon, Hyung Soo Uh, 1997 .

Improving the cell characteristics using arch-active profile in NAND flash memory having 60.nm design rule

Hyungcheol Shin, Il Han Park, Byung-Gook Park, 2008, 2008 IEEE Silicon Nanoelectronics Workshop.

Design and Fabrication of Asymmetric MOSFETs Using a Novel Self-Aligned Structure

Woo Young Choi, Byung-Gook Park, Jong Duk Lee, 2007, IEEE Transactions on Electron Devices.

Investigation of Frequency Dependent Sensitivity of Noise Figure on Device Parameters in 65 nm CMOS

Hyungcheol Shin, Hee-Sauk Jhon, Hakchul Jung, 2009 .

Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2008, IEICE Trans. Electron..

Design and Simulation of Asymmetric MOSFETs

Woo Young Choi, Byung-Gook Park, Jong Duk Lee, 2006, IEICE Trans. Electron..

Reverse-order source/drain formation with double offset spacer (RODOS) for CMOS low-power, high-speed and low-noise amplifiers

Woo Young Choi, Byung-Gook Park, Jong Duk Lee, 2003, ISLPED '03.

Design and optimization of two-bit double-gate nonvolatile memory cell for highly reliable operation

Il Han Park, Ki-Whan Song, Byung-Gook Park, 2006 .

Low power size‐efficient CMOS UWB low‐noise amplifier design

Hyungcheol Shin, Hee-Sauk Jhon, Jongwook Jeon, 2009 .

Application of Area-Saving RF Test Structure on Mobility Extraction

Byung-Gook Park, Jong Duk Lee, Hyungcheol Shin, 2009 .

Implementation of FED with MOSFET-controlled FEA

Jong Duk Lee, Chang Woo Oh, Il Hwan Kim, 1998, Eleventh International Vacuum Microelectronics Conference. IVMC'98 (Cat. No.98TH8382).

Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2009, IEICE Trans. Electron..

3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array

Hyungcheol Shin, Yoon Kim, Byung-Gook Park, 2009, IEICE Trans. Electron..

A New Threshold Voltage Extraction Method for Organic Thin-Film Transistors

Jong Duk Lee, Yoo Chul Kim, Keum-Dong Jung, 2007 .

A New MOSFET Design Concept Using Recessed Channel Structure for Deep Submicron Application

Jong Duk Lee, Young June Park, Woo Hyeong Lee, 1994 .

The Prospects of FPD Market and Technology

Jong Duk Lee, 1997 .

A 2-Bit Recessed Channel Nonvolatile Memory Device With a Lifted Charge-Trapping Node

Il Han Park, Byung-Gook Park, Jong Duk Lee, 2009 .

Reduction of Breakdown Voltage in I-MOS Devices

Woo Young Choi, Byung-Gook Park, Jong Duk Lee, 2006 .

Quantitative Analysis on Voltage Schemes for Reliable Operations of a Floating Gate Type Double Gate Nonvolatile Memory Cell

Hyungcheol Shin, Il Han Park, Jong Duk Lee, 2005 .

A Highly Scalable Split-Gate SONOS Flash Memory with Programmable-Pass and Pure-Select Transistors for Sub-90-nm Technology

Chilhee Chung, Byung-Gook Park, Jong Duk Lee, 2004 .

A new linearity measurement algorithm for sub-micron microwave cmos

Woo Young Choi, Byung-Gook Park, Jong Duk Lee, 2003, Proceedings of the 20th IEEE Instrumentation Technology Conference (Cat. No.03CH37412).

Fabrication of 0.1um Buried Channel and Surface Channel pMOSFETs

Byung-Gook Park, Jong Duk Lee, Tae Jong Yoo, 1997 .

Junction Leakage Characteristics of Shallow Trench Isolation (STI) with Nitrogen Pile-Up Sidewall Oxide(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)

Woo Young Choi, Byung-Gook Park, Jong Duk Lee, 2003 .

A New Substrate Resistance Model of RF MOSFETs

Hyungcheol Shin, Jong Duk Lee, Youngchang Yoon, 2006 .

Optimal Design of FEA (Field Emitter Array) using an Evolution Strategy

Byoungho Lee, Jae-Hoon Jung, Jong Duk Lee, 1997, 10th International Conference on Vacuum Microelectronics.

Various Flash Memory Devices of Novel Design

Byung-Gook Park, Jong Duk Lee, Jang-Gn Yun, 2009 .

Characterization and Design Consideration of 80-nm Self-Aligned N-/P-Channel I-MOS Devices

Woo Young Choi, Byung-Gook Park, Jong Duk Lee, 2006 .

Design of MOSFET - Controlled FED integrated with driver circuits

Jong Duk Lee, Il-Hwan Kim, Jung Hyun Nam, 1999 .

EFFECTS OF HIGH INJECTION BARRIER ON THE BiCMOS INVERTER DELAY

Young-June Park, Jong Duk Lee, Jong-Ho Lee, 1989 .

3D NAND flash memory with laterally-recessed channel (LRC) and connection gate architecture

Byung-Gook Park, Jong Duk Lee, Jang-Gn Yun, 2011 .

Effects of electrical stress on mid-gap interface trap density and capture cross sections in n-MOSFETs characterized by pulsed interface probing measurements

In Man Kang, Byung-Gook Park, Jong Duk Lee, 2004, Microelectron. Reliab..

Challenges in Nanoscale Devices and Breakthrough

Woo Young Choi, Jong Duk Lee, 2005 .

Memory characteristics improvement encouraged by the shape of narrow drain in cone SONOS memory structure

Il Han Park, Byung-Gook Park, Jong Duk Lee, 2008, 2008 IEEE Silicon Nanoelectronics Workshop.

A new 50-nm nMOSFET with side-gates for virtual source-drain extensions

Byung-Gook Park, Jong Duk Lee, Byung Yong Choi, 2002 .

A 32×33 Photo-elements MOS Image Sensor

Jong Duk Lee, Sang Sik Park, Jeong Ok Park, 1987 .

Design and simulation of folded split gate SONOS memory

Il Han Park, Byung-Gook Park, Jong Duk Lee, 2008, 2008 IEEE Silicon Nanoelectronics Workshop.

A New Capacitorless 1T DRAM Cell: Surrounding Gate MOSFET With Vertical Channel (SGVC Cell)

Hyungcheol Shin, Il Han Park, Kangyoon Lee, 2007, IEEE Transactions on Nanotechnology.

MOS varactor modeling for mm-Wave applications

In Man Kang, Hyungcheol Shin, Hakchul Jung, 2008, 2008 Asia-Pacific Microwave Conference.

Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design

Hyungcheol Shin, Jongwook Jeon, Byung-Gook Park, 2009, IEICE Trans. Electron..

Fabrication Process of Cone SONOS Memory Structure

Il Han Park, Byung-Gook Park, Jong Duk Lee, 2008 .

Complete Quasi-Static Modeling of Accumulation Mode MOSFETs

Hyungcheol Shin, Jong Duk Lee, Keum-Dong Jung, 2007 .

Characterization and Design Consideration of I-MOS Devices

Woo Young Choi, Byung-Gook Park, Jong Duk Lee, 2006 .

Dual-Poly Gate Surface Channel 0.1mm CMOSFETs

Byung-Gook Park, Jong Duk Lee, Hyouk Man Kwon, 1997 .

High Sensitivity Signal Charge Detector for CCD Image Sensor

Jong Duk Lee, Chul Min Jung, 1990 .

Cone-Type SONOS Flash Memory

Hyungcheol Shin, Il Han Park, Byung-Gook Park, 2009, IEEE Electron Device Letters.

Analytical Noise Parameter Model of Short-Channel RF MOSFETs

Jongwook Jeon, Byung-Gook Park, Jong Duk Lee, 2007 .

Complementary self-biased scheme for the robust design of CMOS/SET hybrid multi-valued logic

Ki-Whan Song, Sang-Hoon Lee, Byung-Gook Park, 2003, 33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings..

SET/CMOS hybrid process and multiband filtering circuits

Ki-Whan Song, Young-Wug Kim, Yong Kyu Lee, 2005 .

Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation

Byung-Gook Park, Jong Duk Lee, Seongjae Cho, 2009, IEICE Trans. Electron..

Dumbbell-shaped Nanowire with Body Contact Region for Three Dimensional (3D) NAND Flash Memory Application

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2010 .

Electrical and Optical Isolation for Si FED : characterization and Improvement

Hyungcheol Shin, Jong Duk Lee, Jong-Ho Lee, 1997 .

An analytical channel thermal noise model for deep-submicron MOSFETs with short channel effects

Jongwook Jeon, Byung-Gook Park, Jong Duk Lee, 2007 .

Consideration of Bondingwire inductance In the Design of a 5.65 GHz CMOS LNA

Jong Duk Lee, Taehyoun Oh, Yujo Yun, 2006 .

Enhanced Program/Erase Characteristic of Arch Shaped SONOS Flash Memory

Il Han Park, Byung-Gook Park, Jong Duk Lee, 2008 .

Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2007, IEICE Trans. Electron..

A High Performance 0.1mm Inverted-Sidewall Recessed-Channel ( ISRC ) nMOSFET

Jong Duk Lee, Byung-Gook Park, Kuk Jin Chun, 1996 .

Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme

Yoon Kim, Byung-Gook Park, Jong Duk Lee, 2008, IEICE Trans. Electron..

Silicon and metal tip arrays fabricated by LOCOS

Jong Duk Lee, Sang Jik Kwon, Hyung Soo Uh, 1995 .

High Performance Bipolar Transistor with Self-Aligned Recessed Emitter and Selectively Retrograded Collector Profile

Jong Duk Lee, Young June Park, Jong-Ho Lee, 1994 .

A Simple Figure of Merit of RF MOSFET for Low-Noise Amplifier Design

Hyungcheol Shin, Hee-Sauk Jhon, Jongwook Jeon, 2008, IEEE Electron Device Letters.

Full-Swing Pentacene Organic Inverter with Long-Channel Driver and Short-Channel Load

Byung-Gook Park, Jong Duk Lee, Dong-Wook Park, 2006 .

Fabrication and characterization of fin SONOS flash memory with separated double-gate structure

Hyungcheol Shin, Il Han Park, Byung-Gook Park, 2008 .

Gated Twin-Bit (GTB) nonvolatile memory device and its operation

Hyungcheol Shin, Il Han Park, Byung-Gook Park, 2008, 2008 IEEE Silicon Nanoelectronics Workshop.

A Metal-Oxide-Semiconductor Field-Effect Transistor-Contorolled Field Emitter Array

Jong Duk Lee, Dong Hwan Kim, 1997 .

Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory

Hyungcheol Shin, Byung-Gook Park, Jong Duk Lee, 2009, IEICE Trans. Electron..

Dependency of Program Efficiency on Implementation Conditions for NOR Type Silicon-on-Insulator (SOI) Flash Memory

Il Han Park, Byung-Gook Park, Jong Duk Lee, 2008 .

Fabrication of Sub-Half Micron PMOS Device

Jong Duk Lee, Kuk Jin Chun, Yeo Hwan Kim, 1992 .