Woo-Seop Kim

发表

A 4-Gbps/pin transceiver with a multi-level simultaneous bi-directional scheme for serial link applications ☆

Woo-Seop Kim, Jin-Hyun Kim, Chang-Hyun Kim, 2004 .

8Gb 3D DDR3 DRAM using through-silicon-via technology

So-Ra Kim, Hoon Lee, Tae-Kyung Jung, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 6-Gbps/pin Half-Duplex LVDS I/O for High-Speed Mobile DRAM

Young-Hyun Jun, Jin-Hyun Kim, Changhyun Kim, 2005, 2005 IEEE Asian Solid-State Circuits Conference.

An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme

Jin-Young Kim, Changhyun Kim, Hwan-Wook Park, 2006, IEEE Journal of Solid-State Circuits.

A control protocol architecture based on LonTalk protocol for power line data communications

Suki Kim, Lok-Won Kim, Kyeong-Deok Moon, 2002, 2002 Digest of Technical Papers. International Conference on Consumer Electronics (IEEE Cat. No.02CH37300).

BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel

Jung Sunwoo, Young-Chan Jang, Yun-Sang Lee, 2009, IEEE Journal of Solid-State Circuits.

11.8 A 2Gb/s Point-to-Point Heterogeneous Voltage Capable DRAM Interface for Capacity-Scalable

Soo-In Cho, Jung-Hwan Choi, James E. Jaussi, 2004 .

A control network architecture based on EIA-709.1 protocol for power line data communications

Suki Kim, Woo-Seop Kim, Lok-Won Kim, 2002, IEEE Trans. Consumer Electron..

Channel BER Measurement for a 5.8Gb/s/pin unidirectional differential I/O for DRAM application

Jung Sunwoo, Yun-Sang Lee, Sang-Yun Kim, 2008, 2008 IEEE Asian Solid-State Circuits Conference.

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

Young-Hyun Jun, Dukha Park, Sooho Cha, 2009, IEEE Journal of Solid-State Circuits.

A new node architecture based on Lontalk protocol

Suki Kim, Lok-Won Kim, Kyeong-Deok Moon, 2002 .

A 4 Gb/s/pin dual-reference simultaneous bidirectional I/O circuit for memory-bus interface

Suki Kim, Soo-In Cho, Jung-Hwan Choi, 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

BER Simulator Development for Link Compliance Analysis

Changhyun Kim, Jonghoon Kim, Young-Chan Jang, 2008 .

An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme

Kee-Won Kwon, Jung Sunwoo, Jin-Young Kim, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW

Young-Hyun Jun, Dae-Hyun Kim, Young-Sik Kim, 2011, 2011 IEEE International Solid-State Circuits Conference.

Self-calibrating transceiver for source synchronous clocking system with on-chip TDR and swing level control scheme

Joon-Young Park, Changhyun Kim, Young-Chan Jang, 2009, 2009 Symposium on VLSI Circuits.

A 4Gb/s/pin 4-level simultaneous bidirectional I/O using a 500MHz clock for high-speed memory

Suki Kim, Soo-In Cho, Jung-Hwan Choi, 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

A 31ns random cycle VCAT-based 4F2 DRAM with enhanced cell efficiency

Ki-Whan Song, Dukha Park, Yeong-Taek Lee, 2009, 2009 Symposium on VLSI Circuits.

A 40nm 7Gb/s/pin single-ended transceiver with jitter and ISI reduction techniques for high-speed DRAM interface

Young-Hyun Jun, Dong-Min Kim, Young-Sik Kim, 2010, 2010 Symposium on VLSI Circuits.

Bidirectional IO Using a 500MHz Clock for High-Speed Memory

Suki Kim, Soo-In Cho, Jung-Hwan Choi, 2004 .

A 3.6 Gb/s/pin simultaneous bidirectional (SBD) I/O interface for high-speed DRAM

Sung-Woo Shin, Soo-In Cho, Jung-Hwan Choi, 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

Noise immunity improvement in the RESET signal of DDR3 SDRAM memory module

Jun-Dong Cho, Joo-Sun Choi, Woo-Seop Kim, 2013, 2013 IEEE International SOC Conference.

A 0.25-㎛ CMOS 1.6Gbps/pin 4-Level Transceiver Using Stub Series Terminated Logic Interface for High Bandwidth

Suki Kim, Woo-Seop Kim, Jin-Hyun Kim, 2002 .

A 31 ns Random Cycle VCAT-Based 4F $^{2}$ DRAM With Manufacturability and Enhanced Cell Efficiency

Ki-Whan Song, Young-Hyun Jun, Jinyoung Kim, 2010, IEEE Journal of Solid-State Circuits.

A 2Gb/s point-to-point heterogeneous voltage capable DRAM interface for capacity-scalable memory subsystems

Soo-In Cho, R. Mooney, W. Hokenmaier, 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling

Jin-Hyun Kim, Hong-Sun Hwang, Woo-Seop Kim, 2005, IEEE J. Solid State Circuits.