D. Vasudevan

Fault Tolerant Quantum Computation with a New Reversible Gate

P. Lala, J. Parkerson, D. Vasudevan, 2005 .

Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding

Parag K. Lala, James Patrick Parkerson, Dilip P. Vasudevan, 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

Automatic test pattern generation for asynchronous circuits

Dilip Vasudevan, D. Vasudevan, 2012 .

A Partial Scan Based Test Generation for Asynchronous Circuits

Aristides Efthymiou, Dilip P. Vasudevan, A. Efthymiou, 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.

A 6.45 $\mu{\rm W}$ Self-Powered SoC With Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios for Portable Biomedical Systems

Xing Chen, David D. Wentzloff, Benton H. Calhoun, 2015, IEEE Transactions on Biomedical Circuits and Systems.

Online testable reversible logic circuit design using NAND blocks

Parag K. Lala, James Patrick Parkerson, Dilip P. Vasudevan, 2004, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings..

A Reversible MIPS multi-cycle control FSM design

Maziar Goudarzi, Emanuel Popovici, Dilip Vasudevan, 2009, 2009 1st Asia Symposium on Quality Electronic Design.