Michael D. Powell

发表

Dynamically Resizable Instruction Cache: An Energy-Efficient and High-Performance Deep-Submicron Instruction Cache

Kaushik Roy, Babak Falsafi, T. N. Vijaykumar, 2000 .

Reducing leakage in a high-performance deep-submicron instruction cache

Kaushik Roy, T. N. Vijaykumar, Se-Hyun Yang, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Dynamically Resizable Instruction Cache: A Design for an Energy-Efficient and High-Performance Deep-Submicron Instruction Cache

Kaushik Roy, Babak Falsafi, T. N. Vijaykumar, 2000 .

Reducing set-associative cache energy via way-prediction and selective direct-mapping

Kaushik Roy, Amit Agarwal, Babak Falsafi, 2001, MICRO.

Architectural core salvaging in a multi-core processor for hard-error tolerance

Shantanu Gupta, Arijit Biswas, Shubhendu S. Mukherjee, 2009, ISCA '09.

Optimizing replication, communication, and capacity allocation in CMPs

Zeshan Chishti, T. N. Vijaykumar, Zeshan A. Chishti, 2005, 32nd International Symposium on Computer Architecture (ISCA'05).

Optimizing Replication, Communication, and Capacity Allocation in CMPs

T. N. Vijaykumar, Zeshan A. Chishti, Michael D. Powell, 2005, ISCA 2005.

An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches

Kaushik Roy, Babak Falsafi, T. N. Vijaykumar, 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

Resource area dilation to reduce power density in throughput servers

T. N. Vijaykumar, Michael D. Powell, 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

Evaluating Opportunity and Effectiveness of Cache Resizing in Reducing Energy Dissipation

Kaushik Roy, T. N. Vijaykumar, Se-Hyun Yang, 2001 .

Pipeline damping: a microarchitectural technique to reduce inductive noise in supply voltage

T. N. Vijaykumar, Michael D. Powell, 2003, ISCA '03.

Reducing set-associative cache energy via way-prediction and selective direct-mapping

Kaushik Roy, T. N. Vijaykumar, Amit Agarwal, 2001, Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture. MICRO-34.

An Energy-Efficient High-Performance Deep-Submicron Instruction Cache

Kaushik Roy, Babak Falsafi, T. N. Vijaykumar, 2001 .

Reducing register ports for higher speed and lower energy

T. N. Vijaykumar, Michael D. Powell, Il Park, 2002, MICRO.

Microarchitectural techniques for power-related issues in scaled technologies

T. N. Vijaykumar, Michael D. Powell, 2005 .

Achieving uniform performance and maximizing throughput in the presence of heterogeneity

Krishna K. Rangan, Gu-Yeon Wei, David M. Brooks, 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.

CAMP: A technique to estimate per-structure power at run-time using a few simple parameters

Shrirang M. Yardi, Arijit Biswas, Joel S. Emer, 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

Exploiting resonant behavior to reduce inductive noise

T. N. Vijaykumar, Michael D. Powell, 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

Balancing resource utilization to mitigate power density in processor pipelines

T. N. Vijaykumar, Ethan Schuchman, Michael D. Powell, 2005, 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05).

Distance associativity for high-performance energy-efficient non-uniform cache architectures

T. N. Vijaykumar, Zeshan A. Chishti, Michael D. Powell, 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

Heat-and-run: leveraging SMT and CMP to manage power density through the operating system

T. N. Vijaykumar, Michael D. Powell, Mohamed A. Gomaa, 2004, ASPLOS XI.

Exploiting choice in resizable cache design to optimize deep-submicron processor energy-delay

Babak Falsafi, T. N. Vijaykumar, Se-Hyun Yang, 2002, Proceedings Eighth International Symposium on High Performance Computer Architecture.

Reducing register ports for higher speed and lower energy

T. N. Vijaykumar, Michael D. Powell, Il Park, 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..

Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures

Zeshan Chishti, T. N. Vijaykumar, Michael D. Powell, 2003, MICRO.

Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise

T. N. Vijaykumar, Michael D. Powell, 2003, ISLPED '03.

Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories

Kaushik Roy, Babak Falsafi, T. N. Vijaykumar, 2000, ISLPED '00.