Masakazu Kakumu

发表

A high-speed low-power 0.3 /spl mu/m CMOS gate array with variable threshold voltage (VT) scheme

Tadahiro Kuroda, Takayasu Sakurai, Kenji Matsuo, 1996, Proceedings of Custom Integrated Circuits Conference.

for Very Low Operation Voltage

Hiroshi Takahashi, Yasumasa Okamoto, Masakazu Kakumu, 2003 .

Hot-carrier generation in submicrometer VLSI environment

Tetsuya Iizuka, Takayasu Sakurai, Kazutaka Nogami, 1986 .

with Alternating Bit-line Loads

Atsushi Kawasumi, A. Suzuki, Kazunari Ishimaru, 1996 .

1-Mbit virtually static RAM

Tetsuya Iizuka, Takayasu Sakurai, M. Isobe, 1986 .

Multiobjective optimization of VLSI interconnect parameters

Hideki Shibata, Masakazu Kakumu, M. B. Anand, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Work Function Controlled Silicide Technology for Submicron CMOS

Kazuhiko Hashimoto, Masakazu Kakumu, 1984, 1984 Symposium on VLSI Technology. Digest of Technical Papers.

Embedded SRAM with O.5um CMOS Gate Array

Kenji Maeguchi, Makoto Takahashi, M. Uchida, 1990 .

Bipolar installed CMOS technology without any process step increase for high speed cache SRAM

Kazunari Ishimaru, Masakazu Kakumu, Fumiyoshi Matsuoka, 1995, Proceedings of International Electron Devices Meeting.

High Performance Silicided Source/Drain CMOSFET Without Parasitic Effects

Kazuhiko Hashimoto, Masakazu Kakumu, 1984, 1984 Symposium on VLSI Technology. Digest of Technical Papers.

Design Methodology of Deep Submicron CMOS Devices for 1 V Operation (Special Issue on Low-Power LSI Technologies)

M. Kinugawa, Masakazu Kakumu, Hisato Oyamatsu, 1996 .

Precise measurement method of source and drain parasitic resistance and design guideline for scaled MOSFET

Masakazu Kakumu, A. Azuma, T. Asamura, 1994, Proceedings of 1994 VLSI Technology Symposium.

A 4-Mb CMOS SRAM with a PMOS thin-film-transistor load cell

Kenji Maeguchi, T. Yabe, M. Kinugawa, 1990 .

A 36ns 1Mbit Pseudo SRAM with VSRAM mode

Tetsuya Iizuka, Katsuhiko Sato, Takayasu Sakurai, 1987, 1987 Symposium on VLSI Circuits.

Substrate noise influence on circuit performance in variable threshold-voltage scheme

Tadahiro Kuroda, Takayasu Sakurai, Kenji Matsuo, 1996, ISLPED '96.

High-Density Full-CMOS SRAM Cell Technology with a Deep Sub-Micron Spacing between nMOS and pMOSFET (Special Section on High Speed and High Density Multi Functional LSI Memories)

Toshiyuki Kondo, Kazunari Ishimaru, Hidetoshi Koike, 1994 .

FAM 18.7: Hot-Carrier Suppressed VLSI with Submicron Geometry

Takayasu Sakurai, Toshiba Semiconductor, Masakazu Kakumu, 1984 .

Submicron MLDO NMOSFETs for 5V Operation

Kazuhiko Hashimoto, Masakazu Kakumu, Shunji Yokogawa, 1985, 1985 Symposium on VLSI Technology. Digest of Technical Papers.

Cell technology directions for advanced MPUs and other memory-embedded logic devices

M. Kinugawa, Masakazu Kakumu, 1993, Proceedings of IEEE International Electron Devices Meeting.

Process and Device Technologies of CMOS Devices for Low-Voltage Operation (Special Section on Low-Power and Low-Voltage Integrated Circuits)

Masakazu Kakumu, 1993 .

A 1Mb virtually SRAM

Tetsuya Iizuka, Takayasu Sakurai, M. Isobe, 1986, 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Simple and quick turnaround time fabrication process for deep submicrometer CMOS generation

Hidetoshi Koike, Masakazu Kakumu, Fumiyoshi Matsuoka, 1996 .

Hot-carrier suppressed VLSI with submicron geometry

Tetsuya Iizuka, Takayasu Sakurai, Masakazu Kakumu, 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

A high performance MOSFET design with highly controllable gate length and low RC delay multilevel interconnects technology for high speed logic devices

N. Matsunaga, Hideki Shibata, M. Kinugawa, 1995, Proceedings of International Electron Devices Meeting.

Submicron 3D Surface-Orientation-Optimized CMOS Technology

Jun'ichi Matsunaga, Masakazu Kakumu, Masaaki Kinugawa, 1986, 1986 Symposium on VLSI Technology. Digest of Technical Papers.

A 1.5 V high performance mixed signal integration with indium channel for 130 nm technology node

T. Noguchi, Masakazu Kakumu, Eiji Morifuji, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).