Daniel Ziener

发表

Partial reconfiguration on FPGAs in practice — Tools and applications

Jürgen Teich, Walter Stechele, Jim Tørresen, 2012, ARCS 2012.

Netlist-level IP protection by watermarking for LUT-based FPGAs

Jürgen Teich, Daniel Ziener, Moritz Schmid, 2008, 2008 International Conference on Field-Programmable Technology.

New Directions for IP Core Watermarking and Identification

Jürgen Teich, Daniel Ziener, 2010, Dynamically Reconfigurable Architectures.

Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning

Jürgen Teich, Daniel Ziener, Christian Zöllner, 2017, Integr..

Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs

Jürgen Teich, Daniel Ziener, J. Teich, 2009, Int. J. Auton. Adapt. Commun. Syst..

Concepts for Autonomous Control Flow Checking for Embedded CPUs

Jürgen Teich, Daniel Ziener, 2008, ATC.

Apparatus for watermarking software to implement an electronic circuit with a watermark and method and apparatus for watermark detection

Daniel Ziener, Juergen Teich, 2006 .

Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems pdf

Daniel Ziener, 2018, ArXiv.

FPGA-Based Dynamically Reconfigurable SQL Query Processing

Jürgen Teich, Andreas Becher, Daniel Ziener, 2016, ACM Trans. Reconfigurable Technol. Syst..

Using the Power Side Channel of FPGAs for Communication

Jürgen Teich, Daniel Ziener, Florian Baueregger, 2010, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines.

Power Signature Watermarking of IP Cores for FPGAs

Jürgen Teich, Daniel Ziener, J. Teich, 2008, J. Signal Process. Syst..

Concepts for Autonomic Integrated Systems

Norbert Wehn, Jürgen Teich, Walter Stechele, 2007 .

Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning

Jürgen Teich, Daniel Ziener, Bernhard Schmidt, 2014, 2014 IEEE International Parallel & Distributed Processing Symposium Workshops.

A LUT-Based Approximate Adder

Jürgen Teich, Stefan Wildermann, Andreas Becher, 2016, 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP 2014) pdf

Dirk Koch, Daniel Ziener, Frank Hannig, 2014, ArXiv.

Unifying Partitioning and Placement for SAT-Based Exploration of Heterogeneous Reconfigurable SoCs

Jürgen Teich, Stefan Wildermann, Daniel Ziener, 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

Runtime stress-aware replica placement on reconfigurable devices under safety constraints

Michael Glaß, Jürgen Teich, Daniel Ziener, 2011, 2011 International Conference on Field-Programmable Technology.

Throughput Optimizations for FPGA-based Deep Neural Network Inference pdf

Daniel Ziener, Thorbjörn Posewsky, Daniel Ziener, 2018, Microprocess. Microsystems.

Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration

Jürgen Teich, Andreas Becher, Daniel Ziener, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques (abstract only)

Jürgen Teich, Daniel Ziener, Bernhard Schmidt, 2014, FPGA.

Symbolic system-level design methodology for multi-mode reconfigurable systems

Jürgen Teich, Stefan Wildermann, Daniel Ziener, 2013, Des. Autom. Embed. Syst..

FPGA core watermarking based on power signature analysis

Jürgen Teich, Daniel Ziener, 2006, 2006 IEEE International Conference on Field Programmable Technology.

Symbolic design space exploration for multi-mode reconfigurable systems

Jürgen Teich, Stefan Wildermann, Daniel Ziener, 2011, 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

Techniques for Increasing Security and Reliability of IP Cores Embedded in FPGA and ASIC Designs

Daniel Ziener, Daniel Ziener, 2010 .

Proceedings of the Second International Workshop on FPGAs for Software Programmers (FSP 2015) pdf

Dirk Koch, Daniel Ziener, Frank Hannig, 2015, ArXiv.

A Self-Adaptive SEU Mitigation System for FPGAs with an Internal Block RAM Radiation Particle Sensor

Jürgen Teich, Robért Glein, Florian Rittner, 2014, 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines.

Configuration Tampering of BRAM-based AES Implementations on FPGAs

Jürgen Teich, Daniel Ziener, Jutta Pirkl, 2018, 2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

Robustness Analysis of Watermark Verification Techniques for FPGA Netlist Cores

Jürgen Teich, Daniel Ziener, Moritz Schmid, 2010 .

Optimizing FPGA-Based Streaming Applications for Throughput Using Pipelining

Daniel Ziener, Ali Asghar, Rick van Loo, 2019, 2019 International Conference on Field-Programmable Technology (ICFPT).

Identifying FPGA IP-Cores Based on Lookup Table Content Analysis

Jürgen Teich, Daniel Ziener, Stefan Assmus, 2006, 2006 International Conference on Field Programmable Logic and Applications.

Acceleration of SQL Restrictions and Aggregations through FPGA-Based Dynamic Partial Reconfiguration

Jürgen Teich, Daniel Ziener, Christopher Dennl, 2013, 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines.

Autonomic MPSoCs for Reliable Systems

Norbert Wehn, Jürgen Teich, Walter Stechele, 2007 .

Efficient deep neural network acceleration through FPGA-based batch processing

Daniel Ziener, Thorbjörn Posewsky, Daniel Ziener, 2016, 2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs

Jürgen Teich, Stefan Wildermann, Andreas Becher, 2016, 2016 International Conference on Field-Programmable Technology (FPT).

FPGAs for Software Programmers

Dirk Koch, Daniel Ziener, Frank Hannig, 2016 .

Multiplexing methods for power watermarking

Jürgen Teich, Daniel Ziener, Florian Baueregger, 2010, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

Reliability of space-grade vs. COTS SRAM-based FPGA in N-modular redundancy

Jürgen Teich, Andreas Becher, Robért Glein, 2015, 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

A co-design approach for accelerated SQL query processing via FPGA-based data filtering

Jürgen Teich, Klaus Meyer-Wegener, Andreas Becher, 2015, 2015 International Conference on Field Programmable Technology (FPT).

A rapid prototyping system for error-resilient multi-processor systems-on-chip

Norbert Wehn, Jürgen Teich, Walter Stechele, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

On-the-fly Composition of FPGA-Based SQL Query Accelerators Using a Partially Reconfigurable Module Library

Jürgen Teich, Daniel Ziener, Christopher Dennl, 2012, 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines.

A Flexible FPGA-Based Inference Architecture for Pruned Deep Neural Networks

Daniel Ziener, Thorbjörn Posewsky, Daniel Ziener, 2018, ARCS.

An FPGA implementation of a threat-based strategy for Connect6

Jürgen Teich, Moritz Mühlenthaler, Daniel Ziener, 2011, 2011 International Conference on Field-Programmable Technology.

Security in Embedded Hardware

Daniel Ziener, 2019 .

FPGA Versus Software Programming: Why, When, and How?

Dirk Koch, Daniel Ziener, Frank Hannig, 2016, FPGAs for Software Programmers.

Stress-Aware Module Placement on Reconfigurable Devices

Michael Glaß, Jürgen Teich, Daniel Ziener, 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

FPGA-based testbed for timing behavior evaluation of the Controller Area Network (CAN)

Jürgen Teich, Daniel Ziener, Tobias Ziermann, 2012, 2012 International Conference on Reconfigurable Computing and FPGAs.

A Dynamic Reconfigurable Architecture for Hybrid Spiking and Convolutional FPGA-Based Neural Network Designs

Daniel Ziener, Nikolaos S. Alachiotis, Nikolaos Alachiotis, 2021, Journal of Low Power Electronics and Applications.

Increasing Side-Channel Resistance by Netlist Randomization and FPGA-Based Reconfiguration

Benjamin Hettwer, Daniel Ziener, Ali Asghar, 2021, ARC.

Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration

Daniel Ziener, Nikolaos S. Alachiotis, Nikolaos Alachiotis, 2021, 2021 31st International Conference on Field-Programmable Logic and Applications (FPL).

An Energy-Efficient FPGA-based Convolutional Neural Network Implementation

Daniel Ziener, Nikolaos Alachiotis, Hasan Irmak, 2021, 2021 29th Signal Processing and Communications Applications Conference (SIU).

A FLEXIBLE SMART CAMERA SYSTEM BASED ON A PARTIALLY RECONFIGURABLE DYNAMIC FPGA-SOC

Jürgen Teich, Andreas Weichslgartner, Stefan Wildermann, 2011 .