Hsin-Hung Ou

A novel bubble tolerant thermometer-to-binary encoder for flash A/D converter

Bin-Da Liu, Yao-Jen Chuang, Hsin-Hung Ou, 2005, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT)..

Low-Power Circuit Techniques for Low-Voltage Pipelined ADCs Based on Switched-Opamp Architecture

Soon-Jyh Chang, Bin-Da Liu, Hsin-Hung Ou, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A 0.7-V 10-bit 3μW analog-to-digital converter for implantable biomedical applications

Bin-Da Liu, Hsin-Hung Ou, Ya-Chi Chen, 2006, 2006 IEEE Biomedical Circuits and Systems Conference.

A power-efficient 0.8 V, 9-bit, 20-MS/s pipelined ADC with opamp-shared loading-free architecture

Bin-Da Liu, Soon-Jyh Chang, Hsin-Hung Ou, 2008, 2008 International Conference on Communications, Circuits and Systems.

A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach

Bin-Da Liu, Chi-Sheng Lin, Hsin-Hung Ou, 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

A 10-bit 350-Msample/s Nyquist CMOS D/A converter

Bin-Da Liu, Hsin-Hung Ou, Jeng-Dau Chang, 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

A 1-v 9-bit, 2.5-Msample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques

Bin-Da Liu, Hsin-Hung Ou, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Design and Parameter Optimization of a Full-Scale Wastewater Reclamation Plant Including Pretreatment, Electrodialysis Reversal, and Ion Exchange in Steel Manufacturing Processes

Hsin-Hung Ou, Po-Hsun Lin, Yu-Chun Su, 2016 .

A Low-Power Rail-to-Rail 6-bit Flash on a Novel Complementary Average-Value Approach

Bin-Da Liu, Chi-Sheng Lin, Hsin-Hung Ou, 2004 .

A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture

Soon-Jyh Chang, Bin-Da Liu, Hsin-Hung Ou, 2008, IEICE Trans. Electron..