S. Arakawa

High performance copper and low-k interconnect technology fully compatible to 90nm-node SOC application (CMOS4)

K. Sunouchi, M. Inohara, I. Tamura, 2002, Digest. International Electron Devices Meeting,.

Three-dimensional structures for high saturation signals and crosstalk suppression in 1.20 μm pixel back-illuminated CMOS image sensor

Y. Tateshita, T. Hirayama, S. Arakawa, 2013, 2013 IEEE International Electron Devices Meeting.

A manufacturable copper/low-k SiOC/SiCN process technology for 90 nm-node high performance eDRAM

N. Nakamura, Hideki Shibata, Hideshi Miyajima, 2002, Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).