Yuzo Takamatsu

发表

Test Generation for Scan Design Circuits with Tri-State Modules and Bidirectional Terminals

Kozo Kinoshita, Hideo Fujiwara, Takuji Ogihara, 1983, 20th Design Automation Conference Proceedings.

Enhancing multiple fault diagnosis in combinational circuits based on sensitized paths and EB testing

Hiroshi Takahashi, Yuzo Takamatsu, Nobuhiro Yanagida, 1995, Proceedings of the Fourth Asian Test Symposium.

Diagnosis for Multiple Stuck-at Faults by Ambiguous Test Set

Yuzo Takamatsu, Yoshinobu Higami, Yukihiro Yamamoto, 2004 .

BIST based fault diagnosis using ambiguous test set

Yuzo Takamatsu, Hiroshi Takahashi, Yasunori Tsugaoka, 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

Identification of redundant faults in combinational circuits

Yuzo Takamatsu, Tetsuro Minamiyama, 2000, Systems and Computers in Japan.

Generation of Test Sequences with Low Power Dissipation for Sequential Circuits

Yuzo Takamatsu, Yoshinobu Higami, Shin-ya Kobayashi, 2004, IEICE Trans. Inf. Syst..

Fault Analysis of Interconnect Opens in 90nm CMOS ICs with Device Simulator

Masaki Hashizume, Hiroyuki Yotsuyanagi, Yuzo Takamatsu, 2008 .

Electron beam tester aided fault diagnosis for logic circuits based on sensitized paths

Hiroshi Takahashi, Yuzo Takamatsu, Nobuhiro Yanagida, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

On the fault diagnosis in the presence of unknown fault models using pass/fail information

Yuzo Takamatsu, Yoshinobu Higami, Kazuo Yamazaki, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Multiple fault diagnosis by sensitizing input pairs

Hiroshi Takahashi, Yuzo Takamatsu, Nobuhiro Yanagida, 1995, IEEE Design & Test of Computers.

Fault models and test generation for IDDQ testing: embedded tutorial

Kozo Kinoshita, Kewal K. Saluja, Yuzo Takamatsu, 2000, ASP-DAC.

Test cost reduction for logic circuits: Reduction of test data volume and test application time

Yuzo Takamatsu, Yoshinobu Higami, Seiji Kajihara, 2005 .

On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Diagnosis of single gate delay faults in combinational circuits using delay fault simulation

Hiroshi Takahashi, Yuzo Takamatsu, Kwame Osei Boateng, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

New Class of Tests for Open Faults with Considering Adjacent Lines

Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Takahashi, 2009, 2009 Asian Test Symposium.

Improved Forward Test Generation of Sequential Circuits Using Variable-Length Time Frames (Special Issue on VLSI Testing and Testable Design)

Hiroshi Takahashi, Yuzo Takamatsu, Taijiro Ogawa, 1993 .

The Relationship Between the Test Properties and the Fault Models in Diagnosis of Single Bridging Faults by Using Pass/Fail Information

Yuzo Takamatsu, Koji Yamazaki, 2004 .

Reduction of target fault list for crosstalk-induced delay faults by using layout constraints

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

Multiple fault diagnosis in sequential circuits using sensitizing sequence pairs

Hiroshi Takahashi, Yuzo Takamatsu, Nobuhiro Yanagida, 1996, Proceedings of Annual Symposium on Fault Tolerant Computing.

Test generation for redundant faults in combinational circuits by using delay effects

Hiroshi Takahashi, Yuzo Takamatsu, X. Yu, 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).

Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines

Masaki Hashizume, Hiroyuki Yotsuyanagi, Hiroshi Takahashi, 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

A Method of Multiple Fault Diagnosis in Sequential Circuits by Sensitizing Sequence Pairs (Special Issue on Fault-Tolerant Computing)

Hiroshi Takahashi, Yuzo Takamatsu, Nobuhiro Yanagida, 1997 .

Failure analysis of open faults by using detecting/un-detecting information on tests

Yuichi Sato, Hiroshi Takahashi, Yuzo Takamatsu, 2004, 13th Asian Test Symposium.

Generation of tenacious tests for small gate delay faults in combinational circuits

Takashi Watanabe, Hiroshi Takahashi, Yuzo Takamatsu, 1995, Proceedings of the Fourth Asian Test Symposium.

A method to find don't care values in test sequences for sequential circuits

Irith Pomeranz, Yuzo Takamatsu, Yoshinobu Higami, 2003, Proceedings 21st International Conference on Computer Design.

Techniques for finding Xs in test sequences for sequential circuits and applications to test length/power reduction

Yuzo Takamatsu, Yoshinobu Higami, Shin-ya Kobayashi, 2004, 13th Asian Test Symposium.

A method to reduce power dissipation during test for sequential circuits

Yuzo Takamatsu, Yoshinobu Higami, Shin-ya Kobayashi, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

Timing-Aware Diagnosis for Small Delay Defects

Hiroshi Takahashi, Yuzo Takamatsu, Yoshinobu Higami, 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

An alternative method of generating tests for path delay faults using N/sub i/-detection test sets

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2002, 2002 Pacific Rim International Symposium on Dependable Computing, 2002. Proceedings..

Static test compaction for IDDQ testing of bridging faults in sequential circuits

Kozo Kinoshita, Kewal K. Saluja, Yuzo Takamatsu, 2000 .

Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information

Hiroshi Takahashi, Yuzo Takamatsu, Yoshinobu Higami, 2008, IEICE Trans. Inf. Syst..

Modifying test vectors for reducing power dissipation in CMOS circuits

Yuzo Takamatsu, Yoshinobu Higami, Shin-ya Kobayashi, 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.

Test generation for double stuck-at faults

Yuzo Takamatsu, Yoshinobu Higami, Naoko Takahashi, 2001, Proceedings 10th Asian Test Symposium.

A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Enhancing BIST based single/multiple stuck-at fault diagnosis by ambiguous test set

Hiroshi Takahashi, Yuzo Takamatsu, Yoshinobu Higami, 2004, 13th Asian Test Symposium.

Problems and Solutions on IDDQ Testing

Yuzo Takamatsu, Yoshinobu Higami, Shin-ya Kobayashi, 2003 .

Multiple fault diagnosis in combinational circuits using sensitizing input-pairs

Hiroshi Takahashi, Yuzo Takamatsu, Nobuhiro Yanagida, 1995, Systems and Computers in Japan.

Diagnostic test generation for transition faults using a stuck-at ATPG tool

Hiroshi Takahashi, Yuzo Takamatsu, Yoshinobu Higami, 2009, 2009 International Test Conference.

Diagnosis for Open Faults Based on Detecting/Un-detecting Information on Ambiguous Test Set

Hiroshi Takahashi, Yuzo Takamatsu, Yoshinobu Higami, 2005 .

Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Efficiency improvements for multiple fault diagnosis of combinational circuits

Hiroshi Takahashi, Yuzo Takamatsu, N. Yanagida, 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).

Special Issue on Test and Diagnosis of VLSI

Yuzo Takamatsu, 1998 .

Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

Diagnosing Delay Faults in Combinational Circuits under the Ambiguous Delay Model

Hiroshi Takahashi, Yuzo Takamatsu, Kwame Osei Boateng, 1999 .

Multiple Fault Diagnosis for Combinational Circuits by using Sensitizing Input-Pairs and Electron Beam Tester

Hiroshi Takahashi, Yuzo Takamatsu, Nobuhiro Yanagida, 1996 .

Preliminary Analysis of Interconnect Full Open Faults using TEG chips

Masaki Hashizume, Hiroyuki Yotsuyanagi, Yuzo Takamatsu, 2009 .

Static test compaction for IDDQ testing of bridging faults in sequential circuits

Kozo Kinoshita, Kewal K. Saluja, Yuzo Takamatsu, 2000, Systems and Computers in Japan.

Identification of redundant faults in combinational circuits

Yuzo Takamatsu, Tetsuro Minamiyama, 2000 .

Addressing Defect Coverage through Generating Test Vectors for Transistor Defects

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

AN Alternative Test Generation for Path Delay Faults by Using Ni-Detection Test Sets

Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu, 2003 .

Tests for small gate delay faults in combinational circuits and a test generation method

Takashi Watanabe, Hiroshi Takahashi, Yuzo Takamatsu, 1997, Systems and Computers in Japan.

Multiple fault diagnosis in logic circuits using EB tester and multiple/single fault simulators

Hiroshi Takahashi, Yuzo Takamatsu, Nobuhiro Yanagida, 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

Multiple Gate Delay Fault Diagnosis Using Test-Pairs for Marginal Delays

Hiroshi Takahashi, Yuzo Takamatsu, Kwame Osei Boateng, 1998 .

Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Effective Post-BIST Fault Diagnosis for Multiple Faults

Hiroshi Takahashi, Yuzo Takamatsu, Yoshinobu Higami, 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

A general BIST-amenable method of test generation for iterative logic arrays

Hiroshi Takahashi, Yuzo Takamatsu, Kwame Osei Boateng, 2000, Proceedings 18th IEEE VLSI Test Symposium.

Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2008, IEICE Trans. Inf. Syst..

Tests for small gate delay faults in combinational circuits and a test generation method

Takashi Watanabe, Hiroshi Takahashi, Yuzo Takamatsu, 1997 .

On the Effect of Size of Fault Word in Parallel Fault Simulation

Kozo Kinoshita, Yuzo Takamatsu, 1987 .

Test cost reduction for logic circuits: Reduction of test data volume and test application time

Yuzo Takamatsu, Yoshinobu Higami, Seiji Kajihara, 2005, Systems and Computers in Japan.

Fault simulation techniques to reduce IDDQ measurement vectors for sequential circuits

Kozo Kinoshita, Kewal K. Saluja, Yuzo Takamatsu, 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

Test sequence compaction for sequential circuits with reset states

Kozo Kinoshita, Yuzo Takamatsu, Yoshinobu Higami, 2000, Proceedings of the Ninth Asian Test Symposium.

Test generation for sequential circuits using parallel fault simulation with random inputs

Yuzo Takamatsu, Isao Higashi, Tsuyoshi Kodama, 1995, Systems and Computers in Japan.

A Novel Approach for Improving the Quality of Open Fault Diagnosis

Masaki Hashizume, Hiroyuki Yotsuyanagi, Yuzo Takamatsu, 2009, 2009 22nd International Conference on VLSI Design.

Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits

Kozo Kinoshita, Kewal K. Saluja, Yuzo Takamatsu, 2000, J. Electron. Test..

Post-BIST Fault Diagnosis for Multiple Faults

Hiroshi Takahashi, Yuzo Takamatsu, Yoshinobu Higami, 2008, IEICE Trans. Inf. Syst..

A Method of Locating Open Faults on Incompletely Identified Pass/Fail Information

Yuzo Takamatsu, Koji Yamazaki, 2008, IEICE Trans. Inf. Syst..

A new method for diagnosing multiple stuck-at faults using multiple and single fault simulations

Hiroshi Takahashi, Yuzo Takamatsu, Kwame Osei Boateng, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

Simulation-based diagnosis for crosstalk faults in sequential circuits

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2001, Proceedings 10th Asian Test Symposium.

A method of generating tests for marginal delays and delay faults in combinational circuits

Yuzo Takamatsu, Kwame Osei Boateng, Hiroshi Takahashi, 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation

Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu, 2009, IPSJ Trans. Syst. LSI Des. Methodol..

Exponetiation in Finite Fields Using Dual Basis Multiplier

Yuzo Takamatsu, Masakatu Morii, 1990, AAECC.

A Study for Testability of Redundant Faults in Combinational Circuits Using Delay Effects

Hiroshi Takahashi, Yuzo Takamatsu, Xiangqiu Yu, 1995, IEICE Trans. Inf. Syst..

CONT: a concurrent test generation system

Kozo Kinoshita, Yuzo Takamatsu, 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Extended selection of switching target faults in CONT algorithm for test generation

Kozo Kinoshita, Yuzo Takamatsu, 1990 .

On Finding Don't Cares in Test Sequences for Sequential Circuits

Irith Pomeranz, Yuzo Takamatsu, Yoshinobu Higami, 2006, IEICE Trans. Inf. Syst..

Extended selection of switching target faults in CONT algorithm for test generation

Kozo Kinoshita, Yuzo Takamatsu, 1990, J. Electron. Test..

Design of C-testable multipliers based on the modified Booth Algorithm

Hiroshi Takahashi, Yuzo Takamatsu, Kwame Osei Boateng, 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

Compaction of Test Vectors for IDDQ Testing of Sequential Circuits

Kewal K. Saluja, Yuzo Takamatsu, Yoshinobu Higami, 2000 .

Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC

Masaki Hashizume, Hiroyuki Yotsuyanagi, Yuzo Takamatsu, 2009, 2009 22nd International Conference on VLSI Design.

A Method of Generating Tests with Linearity Property for Gate Delay Faults in Combinational Circuits

Hiroshi Takahashi, Yuzo Takamatsu, Kwame Osei Boateng, 1999 .

Improving the Diagnostic Quality of Open Faults

Masaki Hashizume, Hiroyuki Yotsuyanagi, Yuzo Takamatsu, 2008 .