T. Iwamatsu

发表

An SOI-Based 7.5/spl mu/m-Thick 0.15x0.15mm2 RFID Chip

Y. Ohji, M. Usami, A. Sato, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

Analysis of the Delay Distributions of 0,5 µm SOI LSIs

T. Iwamatsu, 1997 .

70 nm SOI-CMOS of 135 GHz f/sub max/ with dual offset-implanted source-drain extension structure for RF/analog and logic applications

T. Iwamatsu, S. Maegawa, S. Maeda, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Bulk-layout-compatible 0.18-/spl mu/m SOI-CMOS technology using body-tied partial-trench-isolation (PTI)

T. Iwamatsu, Masahide Inuishi, T. Ipposhi, 2001 .

Controllable Inverter Delay and Suppressing Vth Fluctuation Technology in Silicon on Thin BOX Featuring Dual Back-Gate Bias Architecture

T. Iwamatsu, T. Ipposhi, H. Oda, 2007, 2007 IEEE International Electron Devices Meeting.

Impact of actively body-bias controlled (ABC) SOI SRAM by using direct body contact technology for low-voltage application

Y. Ohji, T. Iwamatsu, S. Maegawa, 2003, IEEE International Electron Devices Meeting 2003.

16 Mb DRAM/SOI technologies for sub-1 V operation

H. Miyoshi, T. Iwamatsu, M. Inuishi, 1996, International Electron Devices Meeting. Technical Digest.

A Robust SOI SRAM Architecture by using Advanced ABC technology for 32nm node and beyond LSTP devices

M. Yabuuchi, T. Iwamatsu, S. Obayashi, 2007, 2007 IEEE Symposium on VLSI Technology.

Approaches to extra low voltage DRAM operation by SOI-DRAM

T. Iwamatsu, Narumi Sakashita, Masahide Inuishi, 1998 .

An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology

Hideto Hidaka, Kazuyasu Fujishima, T. Iwamatsu, 1994 .

A Novel Low-Power and High-Speed SOI SRAM With Actively Body-Bias Controlled (ABC) Technology for Emerging Generations

Y. Maki, T. Iwamatsu, S. Maegawa, 2008, IEEE Transactions on Electron Devices.

Body bias controlled SOI technology with HTI

T. Iwamatsu, S. Maegawa, Y. Hirano, 2004, International Meeting for Future of Electron Devices, 2004..

High soft-error tolerance body-tied SOI technology with partial trench isolation (PTI) for next generation devices

T. Iwamatsu, S. Maegawa, K. Shiga, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

Impact of 0.18 /spl mu/m SOI CMOS technology using hybrid trench isolation with high resistivity substrate on embedded RF/analog applications

T. Iwamatsu, Koichiro Mashiko, Masahide Inuishi, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

A CAD compatible SOI/CMOS gate array having body-fixed partially-depleted transistors

T. Iwamatsu, S. Maegawa, I. Takimoto, 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

Bulk-layout-compatible 0.18 /spl mu/m SOI-CMOS technology using body-fixed partial trench isolation (PTI)

T. Iwamatsu, Masahide Inuishi, Shigeto Maegawa, 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

Vmin=0.4 V LSIs are the real with silicon-on-thin-buried-oxide (SOTB) — How is the application with "Perpetuum-Mobile" micro-controller with SOTB?

K. Ishibashi, T. Iwamatsu, T. Hiramoto, 2013, 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

A fully logic-process-compatible, 3-transistor, SESO-memory cell featuring 0.1-FIT/Mb soft error, 100-MHz random cycle, and 100-ms retention

T. Iwamatsu, Y. Takahashi, T. Ipposhi, 2008, 2008 IEEE Symposium on VLSI Circuits.

Impact of 0.10 /spl mu/m SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology

T. Iwamatsu, Masahide Inuishi, Shigeto Maegawa, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

Silicon on thin BOX (SOTB) CMOS for ultralow standby power with forward-biasing performance booster

T. Iwamatsu, T. Hiramoto, R. Tsuchiya, 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.

Reduced drain current variability in fully depleted silicon-on-thin-BOX (SOTB) MOSFETs

T. Iwamatsu, T. Hiramoto, H. Oda, 2012, 2012 IEEE Silicon Nanoelectronics Workshop (SNW).

Poly/high-k/SiON gate stack and novel profile engineering dedicated for ultralow-voltage silicon-on-thin-BOX (SOTB) CMOS operation

T. Iwamatsu, T. Hiramoto, H. Oda, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Evaluation of Soft Errors in DRAM and SRAM using Nuclear Microprobe and Neutron Source

T. Iwamatsu, S. Maegawa, M. Inuishi, 2001, 31st European Solid-State Device Research Conference.

ULSI DRAM/SIMOX with stacked capacitor cells for low-voltage operation

Hideto Hidaka, T. Iwamatsu, Takahiro Tsuruda, 1993, Proceedings of IEEE International Electron Devices Meeting.

Substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel SOI MOSFET's

T. Iwamatsu, S. Maegawa, Koichiro Mashiko, 1999 .

Smallest Vth variability achieved by intrinsic silicon on thin BOX (SOTB) CMOS with single metal gate

T. Iwamatsu, T. Ipposhi, R. Tsuchiya, 2008, 2008 Symposium on VLSI Technology.

Design consideration of 0.4V-operation SOTB MOSFET for super low power application

T. Iwamatsu, H. Oda, Y. Inoue, 2011, 2011 International Meeting for Future of Electron Devices.

Feasibility of 0.18 /spl mu/m SOI CMOS technology using hybrid trench isolation with high resistivity substrate for embedded RF/analog applications

T. Iwamatsu, Koichiro Mashiko, Masahide Inuishi, 2001 .

Sub-30-nm PMOSFET using Gas Cluster Ion Beam Boron Doping for 45-nm node CMOS and beyond

T. Iwamatsu, H. Oda, Y. Inoue, 2007, 2007 International Workshop on Junction Technology.

Suppression of die-to-die delay variability of silicon on thin buried oxide (SOTB) CMOS circuits by balanced P/N drivability control with back-bias for ultralow-voltage (0.4 V) operation

K. Ishibashi, T. Iwamatsu, T. Hiramoto, 2013, 2013 IEEE International Electron Devices Meeting.

Direct Measurement of Transient Drain Currents in Partially-depleted SOI NMOSFETs Using a Nuclear Microprobe for Highly Reliable Device Designs

T. Iwamatsu, Hiromichi Takaoka, K. Nakayama, 2000 .

Demonstration of SiC-MOSFET Embedding Schottky Barrier Diode for Inactivation of Parasitic Body Diode

T. Iwamatsu, S. Hino, S. Nakata, 2016, 2016 European Conference on Silicon Carbide & Related Materials (ECSCRM).

CAD-compatible high-speed CMOS/SIMOX technology using field-shield isolation for 1 M gate array

T. Iwamatsu, N. Tsubouchi, Y. Inoue, 1993, Proceedings of IEEE International Electron Devices Meeting.

CAD-compatible high-speed CMOS/SIMOX gate array using field-shield isolation

T. Iwamatsu, Yasuo Inoue, N. Tsubouchi, 1995 .