Oana Boncalo

发表

Performance Enhancement of Serial Based FPGA Probabilistic Fault Emulation Techniques

Ioana Mot, Oana Boncalo, Alexandru Amaricai, 2015, 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Design Trade‐Offs for FPGA Implementation of LDPC Decoders

Oana Boncalo, Alexandru Amaricai, A. Amaricai, 2017 .

Analysis and implementation of on-the-fly stopping criteria for layered QC LDPC decoders

David Declercq, Valentin Savin, Oana Boncalo, 2015, 2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES).

Non-surjective finite alphabet iterative decoders

David Declercq, Valentin Savin, Oana Boncalo, 2016, 2016 IEEE International Conference on Communications (ICC).

Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders

Fakhreddine Ghaffari, David Declercq, Valentin Savin, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Low-precision DSP-based floating-point multiply-add fused for field programmable gate arrays

Oana Boncalo, Alexandru Amaricai, Constantina-Elena Gavriliu, 2014, IET Comput. Digit. Tech..

Variable-Node-Shift Based Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes

Fakhreddine Ghaffari, David Declercq, Valentin Savin, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

Check node unit for LDPC decoders based on one-hot data representation of messages

Fakhreddine Ghaffari, David Declercq, Valentin Savin, 2015 .

Using Cycle-Approximate Simulation for Bus Based Multi-Processor System-On Chip Analysis

Oana Boncalo, Alexandru Amaricai, Alin Dobre, 2012 .

Low-Cost Hardware Infrastructure for Runtime Thread Level Energy Accounting

Rainer Leupers, Dimitrios S. Nikolopoulos, Oana Boncalo, 2016, ARCS.

Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment

Mircea Vladutiu, Oana Boncalo, Alexandru Amaricai, 2007, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007).

Fault Tolerant Digital Data-Path Design via Control Feedback Loops

Oana Boncalo, Alexandru Amaricai, Zsofia Lendek, 2020 .

Configurable FPGA architecture for hardware-software merge sorting

Oana Boncalo, Alexandru Amaricai, Patricia Carla Petrut, 2016, 2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems.

Lightweight Hardware Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes

David Declercq, Valentin Savin, Oana Boncalo, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Two phase reliability analysis of quantum circuits in a block based approach

Oana Boncalo, Alexandru Amaricai, 2009 .

Memory efficient FPGA implementation for flooded LDPC decoder

Ioana Mot, Oana Boncalo, Alexandru Amaricai, 2015, 2015 23rd Telecommunications Forum Telfor (TELFOR).

Layered LDPC decoder in-order message access scheduling: a case study

Oana Boncalo, Alexandru Amaricai, 2020, 2020 IEEE 14th International Symposium on Applied Computational Intelligence and Informatics (SACI).

Reliability Analysis of Qubit Data Movement for Distributed Quantum Computation

Oana Boncalo, Alexandru Amaricai, A. Amaricai, 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

Cost effective FPGA probabilistic fault emulation

Oana Boncalo, Alexandru Amaricai, Emanuel M. Popovici, 2014, 2014 NORCHIP.

Unrolled layered architectures for non-surjective finite alphabet iterative decoders

Valentin Savin, Oana Boncalo, Alexandru Amaricai, 2017, 2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC).

Probabilistic saboteur-based simulated fault injection techniques for low supply voltage interconnects

Oana Boncalo, Alexandru Amaricai, Mircea Popa, 2014, 2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME).

Simulation-Based Assessment of Quantum Circuit Reliability

Oana Boncalo, O. Boncalo, 2007 .

Multi Clock Flooded LDPC Decoding Architecture with Reduced Memory and Interconnect

Ioana Mot, Oana Boncalo, 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

An FPGA sliding window-based architecture harris corner detector

Oana Boncalo, Alexandru Amaricai, Constantina-Elena Gavriliu, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

Ultra High Throughput Unrolled Layered Architecture for QC-LDPC Decoders

Oana Boncalo, Alexandru Amaricai, 2017, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Memory trade-offs in layered self-corrected min-sum LDPC decoders

Valentin Savin, Oana Boncalo, Alexandru Amaricai, 2016 .

Simulated Fault Injection for Quantum Circuits Based on Simulator Commands

Mircea Vladutiu, Oana Boncalo, Alexandru Amaricai, 2007, 2007 4th International Symposium on Applied Computational Intelligence and Informatics.

FPGA implementations of low precision floating point multiply-accumulate

Oana Boncalo, Alexandru Amaricai, Ovidiu Sicoe, 2013 .

On the Redundant Representation of Partial Remainders in Radix-4 SRT Dividers

Oana Boncalo, Alexandru Amaricai, Ovidiu Sicoe, 2017, J. Circuits Syst. Comput..

Cost effective FPGA implementation for hard decision LDPC decoders

Oana Boncalo, Alexandru Amaricai, A. Amaricai, 2016, 2016 24th Telecommunications Forum (TELFOR).

SRT radix-2 dividers with (5,4) redundant representation of partial remainder

Oana Boncalo, Alexandru Amaricai, 2013, 2013 NORCHIP.

Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor

Mircea Vladutiu, Oana Boncalo, Alexandru Amaricai, 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

Template-based QC-LDPC decoder architecture generation

Oana Boncalo, Alexandru Amaricai, Petru Florin Mihancea, 2015, 2015 10th International Conference on Information, Communications and Signal Processing (ICICS).

Quantum circuit's reliability assessment with VHDL-based simulated fault injection

Oana Boncalo, Mihai Udrescu, Mircea Vlăduţiu, 2010, Microelectron. Reliab..

Multi-level probabilistic timing error reliability analysis using a circuit dependent fault map generation

Valentin Savin, Oana Boncalo, Alexandru Amaricai, 2015, 2015 Conference on Design of Circuits and Integrated Systems (DCIS).

Automatic Generation of FPGA Hardware Accelerators for Graphics Applications

Oana Boncalo, Alexandru Amaricai, 2012, PECCS.

Code-design for efficient pipelined layered LDPC decoders with bank memory organization

David Declercq, Valentin Savin, Oana Boncalo, 2018, Microprocess. Microsystems.

Logical fault modeling of source drain short defects for CMOS reversible circuits

Oana Boncalo, Alexandru Amaricai, 2010, Proceedings of the 17th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2010.

Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition

Mircea Vladutiu, Oana Boncalo, Alexandru Amaricai, 2007 .

Variable throughput LDPC decoders using SIMD-based adaptive quantization

Valentin Savin, Oana Boncalo, Alexandru Amaricai, 2016, 2016 39th International Conference on Telecommunications and Signal Processing (TSP).

Multi-Level Simulated Fault Injection for Data Dependent Reliability Analysis of RTL Circuit Descriptions

Oana Boncalo, Alexandru Amaricai, Mircea Popa, 2016 .

A cycle-count-accurate simulation platform with enhanced design exploration capability

Oana Boncalo, Alexandru Amaricai, Alin Dobre, 2012, SimuTools.

Hardware support for performance measurements and energy estimation of OpenRISC processor

Oana Boncalo, Marius Marcu, Lucian Bara, 2015, 2015 IEEE 10th Jubilee International Symposium on Applied Computational Intelligence and Informatics.

Timing error analysis of flooded LDPC decoders

Valentin Savin, Oana Boncalo, Alexandru Amaricai, 2015, 2015 IEEE International Conference on Microwaves, Communications, Antennas and Electronic Systems (COMCAS).

Design Issues and Implementations for Floating-Point Divide–Add Fused

Mircea Vladutiu, Oana Boncalo, Alexandru Amaricai, 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

Configurable Hardware Accelerator Architecture for a Takagi-Sugeno Fuzzy Controller

Oana Boncalo, Alexandru Amaricai, Zsofia Lendek, 2019, 2019 22nd Euromicro Conference on Digital System Design (DSD).

FPGA implementation of very high radix square root with prescaling

Oana Boncalo, Alexandru Amaricai, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

Memory-Centric Flooded LDPC Decoder Architecture Using Non-surjective Finite Alphabet Iterative Decoding

Oana Boncalo, Alexandru Amaricai, Sergiu Nimara, 2018, 2018 21st Euromicro Conference on Digital System Design (DSD).

Memory efficient implementation of self-corrected min-sum LDPC decoder

Valentin Savin, Oana Boncalo, Alexandru Amaricai, 2014, 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Design for dependability in emerging technologies

Mircea Vladutiu, Oana Boncalo, Mihai Udrescu, 2007, JETC.

Exploiting Parallelism in Double Path Adders' Structure for Increased Throughput of Floating Point Addition

Mircea Vladutiu, Oana Boncalo, Alexandru Amaricai, 2007, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007).

Layered LDPC Decoders With Efficient Memory Access Scheduling and Mapping and Built-In Support for Pipeline Hazards Mitigation

David Declercq, Valentin Savin, Oana Boncalo, 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

Using Simulated Fault Injection for Fault Tolerance Assessment of Quantum Circuits

Mircea Vladutiu, Oana Boncalo, Alexandru Amaricai, 2007, 40th Annual Simulation Symposium (ANSS'07).

Probabilistic Gate Level Fault Modeling for Near and Sub-Threshold CMOS Circuits

Jiaoyan Chen, Oana Boncalo, Alexandru Amaricai, 2014, 2014 17th Euromicro Conference on Digital System Design.

FPGA implementation of hybrid fixed point - Floating point multiplication

Oana Boncalo, Alexandru Amaricai, Marius Marcu, 2013, Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2013.

Design of floating point units for interval arithmetic

Mircea Vladutiu, Oana Boncalo, Alexandru Amaricai, 2009, 2009 Ph.D. Research in Microelectronics and Electronics.

Implementation of very high radix division in FPGAs

Oana Boncalo, Alexandru Amaricai, 2012 .

FPGA architecture of multi-codeword LDPC decoder with efficient BRAM utilization

Oana Boncalo, Alexandru Amaricai, Mircea Popa, 2016, 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Cost-efficient FPGA layered LDPC decoder with serial AP-LLR processing

Valentin Savin, Oana Boncalo, Alexandru Amaricai, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

Floating point multiplication rounding schemes for interval arithmetic

Mircea Vladutiu, Oana Boncalo, Alexandru Amaricai, 2008, 2008 International Conference on Application-Specific Systems, Architectures and Processors.

Improving the Performance of the Divide-Add Fused Operation Using Variable Latency Quotient Generation

Oana Boncalo, Alexandru Amaricai, 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

FPGA design of high throughput LDPC decoder based on imprecise Offset Min-Sum decoding

David Declercq, Valentin Savin, Oana Boncalo, 2015, 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS).

Models and implementations of hardware interface modules in a multi-processor system-on-chip simulator

Oana Boncalo, Alexandru Amaricai, Alin Dobre, 2011, 2011 6th IEEE International Symposium on Applied Computational Intelligence and Informatics (SACI).

Reliability analysis of memory centric LDPC decoders under probabilistic storage failures

Oana Boncalo, Alexandru Amaricai, Emanuel M. Popovici, 2016, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Fault modeling and analysis of short defects in CMOS based reversible circuits

Oana Boncalo, Alexandru Amaricai, 2010 .

QC-LDPC Gear-Like Decoder Architecture with Multi-domain Quantization

Oana Boncalo, 2016, 2016 Euromicro Conference on Digital System Design (DSD).

Two phase simulation-based assessment of quantum error correction codes

Mircea Vladutiu, Oana Boncalo, Alexandru Amaricai, 2009, 2009 MIXDES-16th International Conference Mixed Design of Integrated Circuits & Systems.

Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment

Mircea Vladutiu, Oana Boncalo, Alexandru Amaricai, 2007 .

Calibration of CO, NO2, and O3 Using Airify: A Low-Cost Sensor Cluster for Air Quality Monitoring

Oana Boncalo, Marian-Emanuel Ionascu, Philipp Schneider, 2021, Sensors.