Jui-Jen Wu

发表

具有基體偏壓之低雜訊放大器及整合型多相位濾波器之1-V 2.4-GHz低中頻架構前端接收器電路設計

吳重雨, Chung-Yu Wu, 吳瑞仁, 2004 .

An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded Flash Macros

Meng-Fan Chang, Yen-Chen Liu, Wu-Chin Tsai, 2015, IEEE Journal of Solid-State Circuits.

A large σVTH/VDD tolerant zigzag 8T SRAM with area-efficient decoupled differential sensing and fast write-back scheme

Meng-Fan Chang, Hiroyuki Yamauchi, Yuan-Hua Chu, 2010, 2010 Symposium on VLSI Circuits.

A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs

H. Yamauchi, Hsien-Yu Pan, Jui-Jen Wu, 2009, IEEE Journal of Solid-State Circuits.

A Large $\sigma $V$_{\rm TH}$/VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme

Meng-Fan Chang, Hiroyuki Yamauchi, Yuan-Hua Chu, 2011, IEEE Journal of Solid-State Circuits.

A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V$_{\rm TH}$ Read-Port, and Offset Cell VDD Biasing Techniques

Meng-Fan Chang, Shu-Meng Yang, Hiroyuki Yamauchi, 2013, IEEE Journal of Solid-State Circuits.

A 45-nm Dual-Port SRAM Utilizing Write-Assist Cells Against Simultaneous Access Disturbances

Meng-Fan Chang, Quincy Li, Jui-Jen Wu, 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

A differential data aware power-supplied (D2AP) 8T SRAM cell with expanded write/read stabilities for lower VDDmin applications

Meng-Fan Chang, Hiroyuki Yamauchi, Jui-Jen Wu, 2009, 2009 Symposium on VLSI Circuits.

An embedded flash macro with sub-4ns random-read-access using asymmetric-voltage-biased current-mode sensing scheme

Meng-Fan Chang, Sreedhar Natarajan, Wu-Chin Tsai, 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Area-efficient embedded RRAM macros with sub-5ns random-read-access-time using logic-process parasitic-BJT-switch (0T1R) Cell and read-disturb-free temperature-aware current-mode read scheme

Meng-Fan Chang, Heng-Yuan Lee, Yu-Sheng Chen, 2013, 2013 Symposium on VLSI Circuits.

Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme

Meng-Fan Chang, Frederick T. Chen, Ming-Jinn Tsai, 2014, IEEE Journal of Solid-State Circuits.

19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme

Meng-Fan Chang, Sreedhar Natarajan, Yu-Der Chih, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques

Meng-Fan Chang, Shu-Meng Yang, Hiroyuki Yamauchi, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

Low ${\rm VDDmin}$ Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations

Meng-Fan Chang, Yen-Chen Liu, Yu-Der Chih, 2015, IEEE Journal of Solid-State Circuits.

A Differential Data-Aware Power-Supplied (D$^{2}$AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications

Meng-Fan Chang, Hiroyuki Yamauchi, Yung-Chi Chen, 2009, IEEE Journal of Solid-State Circuits.