D. Finan

An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS

S. Borkar, S.R. Vangal, J. Howard, 2008, IEEE Journal of Solid-State Circuits.

A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS

Sriram R. Vangal, Vasantha Erraguntla, Nitin Borkar, 2003, IEEE J. Solid State Circuits.

A 5 GHz floating point multiply-accumulator in 90 nm dual V/sub T/ CMOS

S. Vangal, N. Borkar, S. Mathew, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

FA 18.4: a phase-tolerant 3.8 GB/s data-communication router for a multiprocessor supercomputer backplane

D. Finan, H. Wilson, M. Haycock, 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

90nm Dual VT CMOS

Sriram R. Vangal, Vasantha Erraguntla, Nitin Borkar, 2003 .

Area-efficient linear regulator with ultra-fast load regulation

T. Karnik, P. Hazucha, B.A. Bloechel, 2005, IEEE Journal of Solid-State Circuits.

A 10GHz TCP offload accelerator for 10Gb/s Ethernet in 90nm dual-V/sub T/ CMOS

Sriram R. Vangal, Vasantha Erraguntla, Nitin Borkar, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

14.7 A 10GHz TCP Offload Accelerator for 10Gb/s Ethernet in 90nm Dual-VT CMOS

Sriram R. Vangal, Vasantha Erraguntla, Nitin Borkar, 2003 .

An area-efficient, integrated, linear regulator with ultra-fast load regulation

T. Karnik, P. Hazucha, B. Bloechel, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).